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TMS320DM647 Folha de dados(PDF) 62 Page - Texas Instruments |
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TMS320DM647 Folha de dados(HTML) 62 Page - Texas Instruments |
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62 / 166 page  www.ti.com TMS320DM647/TMS320DM648 Digital Media Processor SPRS372 – MAY 2007 Table 6-4. DM647/DM648 Power and Clock Domains (continued) POWER DOMAIN CLOCK DOMAIN PERIPHERAL/MODULE/USAGE System Domain CLKDIV3 TSIP0 System Domain CLKDIV3 TSIP1 System Domain CLKDIV3 DDR Subsystem System Domain CLKDIV3 Video Port 0 System Domain CLKDIV3 Video Port 1 System Domain CLKDIV3 Video Port 2 System Domain CLKDIV3 Video Port 3 System Domain CLKDIV3 Video Port 4 System Domain CLKDIV3 EMIFA System Domain CLKDIV6 HPI System Domain CLKDIV6 PCI System Domain CLKDIV6 VLYNQ System Domain CLKDIV6 UART System Domain CLKDIV6 I2C System Domain CLKDIV6 TIMER 0 System Domain CLKDIV6 TIMER 1 System Domain CLKDIV6 TIMER 2 System Domain CLKDIV6 TIMER 3 System Domain CLKDIV6 SPI System Domain CLKDIV6 McASP System Domain CLKDIV6 VIC System Domain CLKDIV6 GPIO System Domain CLKDIV6 PLL Controller 1 System Domain CLKDIV6 PLL Controller 2 System Domain CLKDIV6 Config SCR System Domain CLKDIV4 0 Internal EMIFA Clock System Domain CLKDIV4 1 Emulation and Trace System Domain CLKDIV4 2 VICP cop_clk/2 System Domain CLKDIV2 VICP cop_clk Ethernet Subsystem Domain SerDes TXBCLK Ethernet Subsystem The DM647/DM648 architecture is divided into the power and clock domains shown in Table 6-5, which further shows the clock domains and their ratios. Table 6-5. DM647/DM648 Clock Domain Assignment SUBSYSTEM CLOCK DOMAIN DOMAIN CLOCK SOURCE FIXED RATIO VS SYSREFCLK FREQUENCY DSP Subsystem CLKDIV1 PLLC1.REFSYSCLK - Peripherals (CLKDIV3 Domain) CLKDIV3 PLLC1.SYSCLK1 1:3 Emulation/Trace CLKDIV4 1 PLLC1.SYSCLK2 1:4 Peripherals (CLKDIV6 Domain) CLKDIV6 PLLC1.SYSCLK3 1:6 Internal EMIFA Clock CLKDIV4 0 PLLC1.SYSCLK4 1:4 VICP cop_clk/2 CLKDIV4 2 PLLC1.SYSCLK5 1:4 VICP cop_clk CLKDIV2 PLLC1.SYSCLK6 1:2 Peripheral Information and Electrical Specifications 62 Submit Documentation Feedback |
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