TMS320DM647 datasheet(83/166 Pages) TI

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6.7 Reset Controller

6.7.1

Power-on Reset (POR Pin)

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372 – MAY 2007

The reset controller detects the different types of resets supported on the DM647/DM648 devices and

manages the distribution of those resets throughout the device.

The device has several types of resets: power-on reset, warm reset, max reset and system reset.

Table 6-21 explains further the types of reset, the reset initiator, and the effects of each reset on the chip.

See Section 6.7.8 for more information on the effects of each reset on the PLL controllers and their clocks.

Table 6-21. Device-Level Reset Types

TYPE

INITIATOR

EFFECT(s)

Power-on Reset

POR pin

Resets the entire chip including the test and emulation logic.

Resets everything except for the test and emulation logic and the

Warm Reset

RESET pin

Ethernet Subsystem

Max Reset

Emulator

Same as a warm reset

A system reset maintains memory contents and does not reset the

test and emulation circuit and the Ethernet Subsystem. The device

System Reset

Emulator/PCI via the PRST pin

configuration pins are also not re-latched and system reset does not

affect the state of the peripherals (enable/disable).

In addition to device-level global resets, the PSC provides the capability to cause local resets to

peripherals and/or the CPU.

Power-on reset (POR) is initiated by the POR pin and is used to reset the entire chip, including the test

and emulation logic. Power-on reset is also referred to as a cold reset since the device usually goes

through a power-up cycle. During power-up, the POR pin must be asserted (driven low) until the power

supplies have reached their normal operating conditions. Note that a device power-up cycle is not required

to initiate a power-on reset.

The following sequence must be followed during a power-on reset:

1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted

(driven low). While POR is asserted, all pins will be in high-impedance mode. After the POR pin is

deasserted (driven high), all Z-group pins, low-group pins, and high-group pins are set to their reset

state and will remain at their reset state until configured by their respective peripheral. The clock and

reset of each peripheral is determined by the default settings of the power and sleep controller (PSC).

2. Once all the power supplies are within valid operating conditions, the POR pin must remain asserted

(low) for a minimum number of CLKIN2 cycles. The PLL1 controller input clock, CLKIN1, and the PCI

input clock, PCLK, must also be valid during this time. PCLK is needed only if the PCI module is being

used. If the DDR2 memory controller and the Ethernet Subsystem are not needed, CLKIN2 and

REFCLKP/REFCLKN can be tied low. In this case, the POR pin must remain asserted (low) for a

minimum of 256 CLKIN1 cycles after all power supplies have reached valid operating conditions.

Within the low period of the POR pin, the following occurs:

The reset signals flow to the entire chip (including the test and emulation logic), resetting modules

that use reset asynchronously.

The PLL1 controller clocks are started at the frequency of the system reference clock. The clocks

are propagated throughout the chip to reset modules that use reset synchronously. By default,

PLL1 is in reset and unlocked.

The PLL2 controller clocks are started at the frequency of the system reference clock. PLL2 is held

in reset. Since the PLL2 controller always operates in PLL mode, the system reference clock and

all the system clocks are invalid at this point.

The RESETSTAT pin stays asserted (low), indicating the device is in reset.

3. The POR pin may now be deasserted (driven high). When the POR pin is deasserted, the

configuration pin values are latched, and the PLL controllers change their system clocks to their default

divide-down values. PLL2 is taken out of reset and automatically starts its locking sequence. Other

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