TMS320DM647 datasheet(95/166 Pages) TI

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6.9.2

DDR2 Memory Controller Peripheral Register Description(s)

6.9.3

DDR2 Memory Controller Electrical Data/Timing

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372 – MAY 2007

Table 6-27. DDR2 Memory Controller Registers

HEX ADDRESS RANGE

ACRONYM

0x7800 0000

MIDR

DDR2 Memory Controller Module and Revision Register

0x7800 0004

DMCSTAT

DDR2 Memory Controller Status Register

0x7800 0008

SDCFG

DDR2 Memory Controller SDRAM Configuration Register

0x7800 000C

SDRFC

DDR2 Memory Controller SDRAM Refresh Control Register

0x7800 0010

SDTIM1

DDR2 Memory Controller SDRAM Timing 1 Register

0x7800 0014

SDTIM2

DDR2 Memory Controller SDRAM Timing 2 Register

0x7800 0018

Reserved

0x7800 0020

BPRIO

DDR2 Memory Controller Burst Priority Register

0x7800 0024 - 0x7800 004C

Reserved

0x7800 0050 - 0x7800 0078

Reserved

0x7800 007C - 0x7800 00BC

Reserved

0x7800 00C0 - 0x7800 00E0

Reserved

0x7800 00E4

DMCCTL

DDR2 Memory Controller Control Register

0x7800 00E8 - 0x7800 00FC

Reserved

0x7800 0100 - 0x7FFF FFFF

Reserved

The Implementing DDR2 PCB Layout on the TMS320DM647/DM648 DMSoC Application Report

(literature number SPRAAK9) specifies a complete DDR2 interface solution for the DM647/DM648 as well

as a list of compatible DDR2 devices. TI has performed the simulation and system characterization to be

sure all DDR2 interface timings in this solution are met; therefore, no electrical data/timing information is

supplied here for this interface.

NOTE

TI supports only designs that follow the board design guidelines outlined in the application

report, SPRAAA7, cited earlier.

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