ADIN1100CCPZ-R7 datasheet(15/78 Pages) AD

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Data Sheet

ADIN1100

THEORY OF OPERATION

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RMII Interface Mode

RMII mode requires an external 50 MHz clock, which can be

sourced externally from a MAC chip or a reference clock and

applied to the ADIN1100 XTAL_I/CLK_IN pin. The 50 MHz clock is

used for both the transmit and receive interfaces.

The receive data, RXD_1 to RXD_0, transitions synchronously to

the reference clock (REF_CLK). The carrier sense and received

data valid signal (CRS_DV) is a combination of the carrier sense

and RX_DV signals, and is asserted while the receive medium is

not idle. CRS_DV is asserted asynchronously to REF_CLK and

deasserted synchronously.

RX_ER is also synchronous to the reference clock signal

(REF_CLK) and asserted when an error is detected in the received

frame or when a false carrier is detected. RX_ER assertion on a

false carrier can be disabled by software.

Do not configure the MAC interface to RMII in software without

ensuring the required 50 MHz clock is available. See the MAC

Interface Configuration Register for more details on RMII interface

parameters.

Figure 11. RMII MAC PHY Interface Signals

RGMII Interface Mode

For the RGMII receive interface, the ADIN1100 generates a 2.5

MHz RXC signal to synchronize RXD_3 to RXD_0. RX_CTL is

a combination of the RX_DV and RX_ER signals (as described

in Table 8) using both edges of the RXC signal. The ADIN1100

transmits the RX_DV signal on the positive edge of RXC and a

combination (XOR function) of RX_DV and RX_ER on the negative

edge of RXC.

For the RGMII transmit interface, the ADIN1100 generates a 2.5

MHz reference clock on TX_CLK. The MAC transmits the TXD_3

to TXD_0 data on both edges of TXC. TX_CTL is a combination of

the TX_EN and TX_ER signals using both edges of TXC. TX_EN is

transmitted on the positive edge of TXC, and a combination (XOR

function) of TX_EN and TX_ER is transmitted on the negative edge

of TXC.

Figure 12. RGMII MAC PHY Interface Signals

TRANSMIT AMPLITUDE CONFIGURATION

The ADIN1100 supports two transmit amplitude modes of opera-

tion, as follows:

►

1.0 V p-p and 2.4 V p-p mode (high level)

►

1.0 V p-p only mode

The high level transmit operating mode allows the ADIN1100 to

support both voltage levels. The operating level can then be auto-

matically configured during autonegotiation (if enabled) based on

the link partner capabilities.

The mode of operation is configured through the TX2P4_EN hard-

ware configuration pin signal (see the Transmit Amplitude section).

The ADIN1100 also configures the default value for the transmit

level register bits used for the autonegotiation process based on the

level configured with the RX_D0/ TX2P4_EN pin (see the Transmit

Amplitude Advertisement section).

The ADIN1100 is configured in high level transmit operating mode

by default if the RX_D0/TX2P4_EN pin is left floating (internal

pull-down resistor).

MASTER/SLAVE CONFIGURATION

The 10BASE-T1L standard uses a master/slave clock scheme.

This scheme is commonly used in full duplex transceiver standards

with echo cancellation. One PHY is designated as the master, and

the other PHY as the slave. Autonegotiation is used to determine

which PHY is the master and which is the slave. Master and slave

assignment does not generally matter.

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