ADIN1100CCPZ-R7 datasheet(69/78 Pages) AD

69 / 78 page

Data Sheet

ADIN1100

ETHERNET CLAUSE 45 REGISTER DETAILS

analog.com

Rev. 0 | 69 of 78

Table 111. Bit Descriptions for MMD2_STATUS

Bits

Bit Name

Description

Reset

Access

[15:14]

MMD2_STATUS

Vendor Specific MMD 2 Status.

0x2

10: device responding at this address.

11: no device responding at this address.

01: no device responding at this address.

00: no device responding at this address.

[13:0]

RESERVED

Reserved.

0x0

PHY SUBSYSTEM INTERRUPT STATUS REGISTER

Device Address: 0x1F; Register Address: 0x0011, Reset: 0x0000, Name: PHY_SUBSYS_IRQ_STATUS

This address can be read to check which interrupt events have occurred since the last time it was read. Each bit goes high when the associated

event occurs and then latches high until it is unlatched by reading. The bits of PHY_SUBSYS_IRQ_STATUS go high even when the associated

bits in PHY_SUBSYS_IRQ_MASK are not set. A reserved interrupt being triggered indicates a fatal error in the system.

Table 112. Bit Descriptions for PHY_SUBSYS_IRQ_STATUS

Bits

Bit Name

Description

Reset

Access

RESERVED

Reserved.

0x0

R LH

MAC_IF_FC_FG_IRQ_LH

MAC Interface Frame Checker/Generator Interrupt.

0x0

R LH

MAC_IF_EBUF_ERR_IRQ_LH

MAC Interface Buffers Overflow/Underflow Interrupt.

0x0

R LH

RESERVED

Reserved.

0x0

R LH

AN_STAT_CHNG_IRQ_LH

Autonegotiation Status Change Interrupt.

0x0

R LH

[10:2]

RESERVED

Reserved.

0x0

R LH

LINK_STAT_CHNG_LH

Link Status Change.

0x0

R LH

RESERVED

Reserved.

0x0

R LH

PHY SUBSYSTEM INTERRUPT MASK REGISTER

Device Address: 0x1F; Register Address: 0x0021, Reset: 0x2402, Name: PHY_SUBSYS_IRQ_MASK

Controls whether or not the interrupt signal is asserted in response to various events.

Table 113. Bit Descriptions for PHY_SUBSYS_IRQ_MASK

Bits

Bit Name

Description

Reset

Access

RESERVED

Reserved.

0x0

R/W SC

MAC_IF_FC_FG_IRQ_EN

Enable MAC Interface Frame Checker/Generator Interrupt.

0x0

R/W

MAC_IF_EBUF_ERR_IRQ_EN

Enable MAC Interface Buffers Overflow/Underflow Interrupt.

0x1

R/W

RESERVED

Reserved.

0x0

R/W

AN_STAT_CHNG_IRQ_EN

Enable Autonegotiation Status Change Interrupt.

0x0

R/W

[10:2]

RESERVED

Reserved.

0x100

R/W

LINK_STAT_CHNG_IRQ_EN

Enable Link Status Change Interrupt.

0x1

R/W

RESERVED

Reserved.

0x0

R/W

FRAME CHECKER ENABLE REGISTER

Device Address: 0x1F; Register Address: 0x8001, Reset: 0x0001, Name: FC_EN

This register is used to enable the frame checker. The frame checker analyzes the received frames from either the MAC interface or the PHY

(see the FC_TX_SEL register) to report the number of frames received, CRC errors, and various other frame errors. The frame checker frame

and error counter registers count these events.

ADIN1100CCPZ-R7 Folha de dados(PDF) 69 Page - Analog Devices

ADIN1100CCPZ-R7 Folha de dados(HTML) 69 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

Folha de dados Download

Ligação URL