ADIN1100CCPZ-R7 datasheet(61/78 Pages) AD

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Data Sheet

ADIN1100

ETHERNET CLAUSE 45 REGISTER DETAILS

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Rev. 0 | 61 of 78

Table 89. Bit Descriptions for CRSM_IRQ_STATUS

Bits

Bit Name

Description

Reset

Access

CRSM_SW_IRQ_LH

Software Requested Interrupt Event.

0x0

R LH

[14:13]

RESERVED

Reserved.

0x0

CRSM_HRD_RST_IRQ_LH

Hardware Reset Interrupt.

0x1

R LH

[11:0]

RESERVED

Reserved.

0x0

R LH

SYSTEM INTERRUPT MASK REGISTER

Device Address: 0x1E; Register Address: 0x0020, Reset: 0x1FFE, Name: CRSM_IRQ_MASK

Controls whether or not the interrupt signal is asserted in response to various events.

Table 90. Bit Descriptions for CRSM_IRQ_MASK

Bits

Bit Name

Description

Reset

Access

CRSM_SW_IRQ_REQ

Software Interrupt Request. Software can set this bit to generate an interrupt for system level

testing. This bit always reads as 0 because it is self clearing.

0x0

R/W SC

[14:13]

RESERVED

Reserved.

0x0

CRSM_HRD_RST_IRQ_EN

Enable Hardware Reset Interrupt. Note that writing a 0 to this bit does not mask the interrupt

because this bit is initialized when a hardware reset occurs.

0x1

R/W

[11:0]

RESERVED

Reserved.

0xFFE

R/W

SOFTWARE RESET REGISTER

Device Address: 0x1E; Register Address: 0x8810, Reset: 0x0000, Name: CRSM_SFT_RST

Table 91. Bit Descriptions for CRSM_SFT_RST

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

CRSM_SFT_RST

Software Reset Register. The software reset bit allows the chip to be reset. When this bit is set, the chip fully

initializes, almost equivalent to a hardware reset.

0x0

R/W SC

SOFTWARE POWER-DOWN CONTROL REGISTER

Device Address: 0x1E; Register Address: 0x8812, Reset: 0x0000, Name: CRSM_SFT_PD_CNTRL

Table 92. Bit Descriptions for CRSM_SFT_PD_CNTRL

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

CRSM_SFT_PD

Software Power-Down. The software power-down register puts the chip in a lower power mode. In this

mode, most of the circuitry is switched off. However, MDIO access to all registers is still possible. The

default value for this register is configurable via the RX_DV/RX_CTL/SWPD_EN pin. This pin allows the

chip to be held in power-down mode until an appropriate software initialization is performed.

Pin dependent

R/W

PHY SUBSYSTEM RESET REGISTER

Device Address: 0x1E; Register Address: 0x8814, Reset: 0x0000, Name: CRSM_PHY_SUBSYS_RST

Table 93. Bit Descriptions for CRSM_PHY_SUBSYS_RST

Bits

Bit Name

Description

Reset

Access

[15:1]

RESERVED

Reserved.

0x0

CRSM_PHY_SUBSYS_RST

PHY Subsystem Reset. The PHY subsystem reset register allows a managed subsystem reset to

be initiated. When the PHY subsystem is reset, normal operation resumes, and the bit self clears.

0x0

R/W SC

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