ADIN1100CCPZ-R7 datasheet(24/78 Pages) AD

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Data Sheet

ADIN1100

HARDWARE CONFIGURATION PINS

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Rev. 0 | 24 of 78

on the MAC interface). An external pull-up resistor or external host

control via a GPIO must be used to select the media converter

operation in RMII mode.

Table 16. Media Converter Selection (Hardware Configuration)

MEDIA_CNV

Media Converter Selection

Normal PHY operation

Media converter operation

PHY Address Configuration

The ADIN1100 PHY address can be configured using three pins:

►

RXD_2/PHYAD_0

►

RXD_3/PHYAD_1

►

LINK_ST/PHYAD_2

These are two-level configuration pins, which means that it is possi-

ble to configure the ADIN1100 to any of the eight available PHY

addresses. The PHY address pins have weak internal pull-down

resistors. Thus, by default, the ADIN1100 is configured with PHY

Address 0x0.

Particular attention is required if these three pins are used in

managed applications and connected to an external host controller

because the PHY address is set after power-up, hardware reset, or

software reset.

Software Power-Down After Reset

The SWPD_EN hardware configuration pin signal is shared with the

RX_DV signal and is used to enable or disable the software pow-

er-down after reset feature. The power-down bit (CRSM_SFT_PD)

is set based on the SWPD_EN signal status during power-up,

hardware reset, or software reset. CRSM_SFT_PD can also be

set using the MDIO interface to enable software power-down after

reset.

The RX_DV/RX_CTL/SWPD_EN pin has a weak internal pull-down

resistor. Thus, by default, the ADIN1100 is configured with software

power-down after reset enabled.

When software power-down after reset is enabled, the ADIN1100

enters software power-down after power-up, hardware reset, or

software reset. Software power-down provides a lower power mode

where most of the ADIN1100 internal modules are turned off.

The ADIN1100 can be configured to exit power-down by setting the

CRSM_SFT_PD bit to 0 using the MDIO interface.

Following a power-up, hardware reset, or software reset, and if

autonegotiation is enabled and software power-down after reset is

disabled, the ADIN1100 starts autonegotiation and tries to bring up

a link.

Table 17. Software Power-Down (Hardware Configuration)

SWPD_EN

Software Power-Down Configuration

PHY in software power-down after reset

PHY not in software power-down

Master/Slave Preference

The MS_SEL hardware configuration pin signal is shared with the

RXD_1 signal and configures the default master/slave selection. If

MS_SEL is pulled low during power-up, hardware reset, or software

reset, the device is configured by default to prefer slave. If MS_SEL

is pulled high during power-up, hardware reset, or software reset,

the device is configured by default to prefer master.

The RXD_1/MS_SEL pin has a weak internal pull-down resistor.

Thus, by default, the ADIN1100 is configured to prefer slave.

The MS_SEL hardware configuration pin signal configures the

default setting of the autonegotiation master/slave configuration

setting of the master slave configuration register bit (CFG_MST),

which is used when autonegotiation is disabled.

The AN_ADV_MST and CFG_MST bits can be modified using the

MDIO interface but return to their default values set by the MS_SEL

hardware configuration pin signal after power-up, hardware reset,

or software reset.

Table 18. Master/Slave Selection (Hardware Configuration)

MS_SEL

Master/Slave Selection

Prefer slave selection

Prefer master selection

Transmit Amplitude

The TX2P4_EN hardware configuration pin signal is shared with

the RXD_0 signal and is used to configure the default transmit

amplitude mode. The transmit amplitude mode is defined by the

pin status during power-up, hardware reset, or software reset as

defined in Table 19.

The TX2P4_EN hardware configuration pin signal configures

the default setting of the high voltage transmit ability bit

(B10L_TX_LVL_HI_ABLE).

The RXD_0/TX2P4_EN pin has a weak internal pull-down resistor.

Thus, by default, the ADIN1100 is configured to support both 1.0 V

p-p and 2.4 V p-p voltage levels.

If the RXD_0/TX2P4_EN pin is strapped high (1.0 V p-p only), the

associated register cannot be changed through the MDIO interface.

That is, 2.4 V p-p operation is not possible if the ADIN1100 has

been hardware pin configured only for 1.0 V p-p.

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