ADIN1100CCPZ-R7 datasheet(71/78 Pages) AD

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Data Sheet

ADIN1100

ETHERNET CLAUSE 45 REGISTER DETAILS

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Rev. 0 | 71 of 78

Table 118. Bit Descriptions for FC_FRM_CNT_H

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_FRM_CNT_H

Bits[31:16] of Latched Copy of the Number of Received Frames.

0x0

FRAME CHECKER COUNT LOW REGISTER

Device Address: 0x1F; Register Address: 0x800A, Reset: 0x0000, Name: FC_FRM_CNT_L

This register is a latched copy of Bits[15:0] of the 32-bit receive frame counter register. When the receive error counter (RX_ERR_CNT) is read,

the receive frame counter register is latched so that the error count and receive frame count are synchronized.

Table 119. Bit Descriptions for FC_FRM_CNT_L

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_FRM_CNT_L

Bits[15:0] of Latched Copy of the Number of Received Frames.

0x0

FRAME CHECKER LENGTH ERROR COUNT REGISTER

Device Address: 0x1F; Register Address: 0x800B, Reset: 0x0000, Name: FC_LEN_ERR_CNT

This register is a latched copy of the frame length error counter register. This register is a count of received frames with a length error status.

When the receive error counter (RX_ERR_CNT) is read, the frame length error counter register is latched, which ensures that the frame length

error count and receive frame count are synchronized.

Table 120. Bit Descriptions for FC_LEN_ERR_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_LEN_ERR_CNT

Latched Copy of the Frame Length Error Counter.

0x0

FRAME CHECKER ALIGNMENT ERROR COUNT REGISTER

Device Address: 0x1F; Register Address: 0x800C, Reset: 0x0000, Name: FC_ALGN_ERR_CNT

This register is a latched copy of the frame alignment error counter register. This register is a count of received frames with an alignment error

status. When the receive error counter (RX_ERR_CNT) is read, the alignment error counter is latched, which ensures that the frame alignment

error count and the receive frame count are synchronized.

Table 121. Bit Descriptions for FC_ALGN_ERR_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_ALGN_ERR_CNT

Latched Copy of the Frame Alignment Error Counter.

0x0

FRAME CHECKER SYMBOL ERROR COUNT REGISTER

Device Address: 0x1F; Register Address: 0x800D, Reset: 0x0000, Name: FC_SYMB_ERR_CNT

This register is a latched copy of the symbol error counter register. This register is a count of received frames with both RX_ER and RX_DV set.

When the receive error counter (RX_ERR_CNT) is read, the symbol error count is latched, which ensures that the symbol error count and the

frame receive count are synchronized.

Table 122. Bit Descriptions for FC_SYMB_ERR_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_SYMB_ERR_CNT

Latched Copy of the Symbol Error Counter.

0x0

FRAME CHECKER OVERSIZED FRAME COUNT REGISTER

Device Address: 0x1F; Register Address: 0x800E, Reset: 0x0000, Name: FC_OSZ_CNT

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