SST26VF040A-80ISLASHMFVAO datasheet(62/73 Pages) MICROCHIP

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DS20006292B-page 62

SST26VF040A

3AH

A20:A16

08H

(1-1-4) Fast Read Number of Wait states (dummy clocks) needed before

valid output

01000b: 8 dummy bits are needed with a single input opcode & address and

quad output data Fast Read instruction.

A23:A21

(1-1-4) Fast Read Number of Mode Bits

000b: No mode bits are needed with a single input opcode & address and

quad output data Fast Read instruction.

3BH

A31:A24

6BH

(1-1-4) Fast Read Opcode

Opcode for single input opcode & address and quad output data Fast Read

instruction.

JEDEC Flash Parameter Table: 4th DWORD

3CH

A4:A0

08H

(1-1-2) Fast Read Number of Wait states (dummy clocks) needed before

valid output

01000b: 8 dummy clocks are needed with a single input opcode, address

and dual output data Fast Read instruction.

A7:A5

(1-1-2) Fast Read Number of Mode Bits

000b: No mode bits are needed with a single input opcode & address and

quad output data Fast Read instruction.

3DH

A15:A8

3BH

(1-1-2) Fast Read Opcode

Opcode for single input opcode & address and dual output data Fast Read

instruction.

3EH

A20:A16

80H

(1-2-2) Fast Read Number of Wait states (dummy clocks) needed before

valid output

00000b: 0 clocks of dummy cycle.

A23:A21

(1-2-2) Fast Read Number of Mode Bits (in clocks)

100b: 4 clocks of mode bits are needed.

3FH

A31:A24

BBH

(1-2-2) Fast Read Opcode

Opcode for single input opcode, dual input address, and dual output data

Fast Read instruction.

JEDEC Flash Parameter Table: 5th DWORD

40H

FEH

Supports (2-2-2) Fast Read

Device supports dual input opcode & address and dual output data Fast

Read.

0: (2-2-2) Fast Read NOT supported

1: (2-2-2) Fast Read supported

A3:A1

Reserved. Bits default to all 1’s.

Supports (4-4-4) Fast Read

Device supports Quad input opcode & address and quad output data Fast

Read.

0: (4-4-4) Fast Read NOT supported

1: (4-4-4) Fast Read supported

A7:A5

Reserved. Bits default to all 1’s.

41H

A15:A8

FFH

Reserved. Bits default to all 1’s.

42H

A23:A16

FFH

Reserved. Bits default to all 1’s.

43H

A31:A24

FFH

Reserved. Bits default to all 1’s.

JEDEC Flash Parameter Table: 6th DWORD

44H

A7:A0

FFH

Reserved. Bits default to all 1’s.

45H

A15:A8

FFH

Reserved. Bits default to all 1’s.

TABLE 11-1:

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (SHEET 4 OF 13)

Address

Bit

Address

Data

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