SST26VF040A-80ISLASHMFVAO datasheet(18/73 Pages) MICROCHIP

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DS20006292B-page 18

SST26VF040A

FIGURE 5-5:

RESET QUAD I/O SEQUENCE (SQI)

5.6

High-Speed Read

The High-Speed Read instruction, 0BH, is supported in

both SPI bus protocol and SQI protocol. This instruc-

tion supports frequencies of up to 104 MHz from

2.7V-3.6V and up to 80 MHz from 2.3V-3.6V. On

power-up, the device is set to use SPI.

Initiate High-Speed Read by executing an 8-bit

command, 0BH, followed by address bits A[23:0] and a

dummy byte. CE# must remain active-low for the

duration of the High-Speed Read cycle. See Figure 5-6

for the High-Speed Read sequence for SPI bus

protocol.

FIGURE 5-6:

HIGH-SPEED READ SEQUENCE (SPI) (C[1:0] = 0BH)

In SQI protocol, the host drives CE# low then sends

one High-Speed Read command cycle, 0BH, followed

by three address cycles, a Set Mode configuration

cycle, and two dummy cycles. Each cycle is two nibbles

(clocks) long, Most Significant nibble first.

After the dummy cycles, the device outputs data on the

falling edge of the SCK signal starting from the

specified address location. The device continually

streams data output through all addresses until

terminated by a low-to-high transition on CE#. The

internal Address Pointer automatically increments until

the highest memory address is reached, at which point

the Address Pointer returns to address location

000000H. During this operation, blocks that are

read-locked will output data 00H.

The Set Mode Configuration bit M[7:0] indicates if the

next instruction cycle is another SQI High-Speed Read

command.

When M[7:0] = AXH, the device expects the next

continuous instruction to be another read command,

0BH, and does not require the opcode to be entered

again. The host may initiate the next read cycle by

driving CE# low, then sending the 4-bit input for

address A[23:0],

followed

the

Set

Mode

Configuration bits M[7:0], and two dummy cycles. After

the two dummy cycles, the device outputs the data

starting from the specified address location. There are

no restrictions on address location access.

When M[7:0] is any value other than AXH, the device

expects the next instruction initiated to be a command

instruction. To reset/exit the Set Mode configuration,

execute the Reset Quad I/O command, FFH. While in

the Set Mode configuration, the RSTQIO command will

only return the device to a state where it can accept a

new command instruction. An additional RSTQIO is

required to reset the device to SPI mode. See

Figure 5-10 for the SPI Quad I/O Mode Read sequence

when M[7:0] = AXH.

MODE 3

SCK

SIO[3:0]

CE#

MODE 0

CE#

SO/SIO1

SI/SIO0

SCK

ADD.

012 34 5 6 7 8

ADD.

High-Impedance

15 16

23 24

31 32

39 40

47 48

55 56

63 64

N+2

N+3

N+4

N+1

MSB

MODE 0

MODE 3

DOUT

71 72

DOUT

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