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SST26VF040A-80I/MFVAO Folha de dados(PDF) 36 Page - Microchip Technology |
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SST26VF040A-80I/MFVAO Folha de dados(HTML) 36 Page - Microchip Technology |
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36 / 73 page ![]() 2020-2021 Microchip Technology Inc. DS20006292B-page 36 SST26VF040A 5.32 Write Disable (WRDI) The Write Disable (WRDI) instruction sets the Write Enable Latch bit in the STATUS register to ‘0’, prevent- ing write operations. The WRDI instruction is ignored during any internal write operations. Any write opera- tion started before executing WRDI will complete. Drive CE# high before executing WRDI. To execute a Write Disable, the host drives CE# low, sends the Write Disable command cycle (04H), then drives CE# high. See Figures 5-36 and 5-37. FIGURE 5-36: WRITE DISABLE (WRDI) SEQUENCE (SQI) FIGURE 5-37: WRITE DISABLE (WRDI) SEQUENCE (SPI) MODE 3 0 1 SCK SIO[3:0] CE# 04 MODE 0 CE# SO SI SCK 0 1 234 5 6 7 04 High-Impedance MODE 0 MODE 3 MSB |
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