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SST26VF040A-80I/MFVAO Folha de dados(PDF) 33 Page - Microchip Technology

Nome de Peças SST26VF040A-80I/MFVAO
Descrição Electrónicos  2.5V/3.0V 4-Mbit Serial Quad I/O??(SQI?? Flash Memory
PDF  73 Pages
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Fabricante Electrônico  MICROCHIP [Microchip Technology]
Página de início  http://www.microchip.com
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 2020-2021 Microchip Technology Inc.
DS20006292B-page 33
SST26VF040A
5.28
Lockout Security ID
The Lockout Security ID instruction prevents any future
changes to the Security ID, and is supported in both
SPI and SQI modes. Prior to the operation, execute
WREN.
To execute a Lockout SID, the host drives CE# low,
sends the Lockout Security ID command cycle (85H),
then drives CE# high. Poll the BUSY bit in the software
STATUS register, or wait TPSID for the completion of the
Lockout Security ID operation.
5.29
Read STATUS Register (RDSR)
and Read Configuration Register
(RDCR)
The Read STATUS Register (RDSR) and Read Config-
uration Register (RDCR) commands output the con-
tents of the STATUS and Configuration registers.
These commands function in both SPI and SQI modes.
The STATUS register may be read at any time, even
during a write operation. When a write is in progress,
poll the BUSY bit before sending any new commands
to assure that the new commands are properly
received by the device.
To read the STATUS or Configuration registers, the
host drives CE# low, then sends the Read STATUS
Register command cycle (05H) or the Read Configura-
tion Register command (35H). A dummy cycle is
required in SQI mode. Immediately after the command
cycle, the device outputs data on the falling edge of the
SCK signal. The data output stream continues until ter-
minated by a low-to-high transition on CE#. See
Figures 5-30 and 5-31 for the instruction sequence.
FIGURE 5-30:
READ STATUS REGISTER AND READ CONFIGURATION REGISTER SEQUENCE
(SQI)
FIGURE 5-31:
READ STATUS REGISTER AND READ CONFIGURATION REGISTER SEQUENCE
(SPI)
TABLE 5-5:
PROGRAM SECURITY ID
Program Security ID
Address Range
Unique ID Preprogrammed at Factory
0000-000FH
User-Programmable
0010H-07FFH
Note:
MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = 05H or 35H
MODE 3
0
SCK
SIO[3:0]
CE#
C1 C0
MODE 0
2
XX
MSN LSN
4
H0 L0
6
H0 L0
8
H0 L0
Dummy
STATUS ByteSTATUS Byte
STATUS Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MODE 3
SCK
SI
SO
CE#
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
05 or 35H
MODE 0
High-Impedance
STATUS or Configuration
Register Out
MSB
MSB



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