SST26VF040A-80ISLASHMFVAO datasheet(23/73 Pages) MICROCHIP

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DS20006292B-page 23

SST26VF040A

5.12

SPI Dual Output Read

The SPI Dual Output Read instruction supports

frequencies of up to 104 MHz from 2.7V-3.6V and up to

80 MHz from 2.3V-3.6V. Initiate SPI Dual Output Read

by executing an 8-bit command, 3BH, followed by

address bits A[23:0] and a dummy byte. CE# must

remain active-low for the duration of the SPI Dual

Output Read operation. See Figure 5-13 for the SPI

Dual Output Read sequence.

Following the dummy byte, SST26VF040A outputs

data from SIO[1:0] starting from the specified address

location. The device continually streams data output

through all addresses until terminated by a low-to-high

transition on CE#. The internal Address Pointer

automatically increments until the highest memory

address is reached, at which point the Address Pointer

returns to the beginning of the address space.

FIGURE 5-13:

FAST READ, DUAL-OUTPUT SEQUENCE

5.13

SPI Dual I/O Read

The SPI Dual I/O Read (SDIOR) instruction supports up

to 80 MHz frequency. Initiate SDIOR by executing an

8-bit command, BBH. The device then switches to 2-bit

I/O mode for address bits A[23:0], followed by the Set

Mode Configuration bits M[7:0]. CE# must remain

active-low for the duration of the SPI Dual I/O Read.

See Figure 5-14 for the SPI Dual I/O Read sequence.

Following the Set Mode Configuration bits, the

SST26VF040A outputs data from the specified address

location. The device continually streams data output

through all addresses until terminated by a low-to-high

transition on CE#. The internal Address Pointer

automatically increments until the highest memory

address is reached, at which point the Address Pointer

returns to the beginning of the address space.

The Set Mode Configuration bit M[7:0] indicates if the

next instruction cycle is another SPI Dual I/O Read

command. When M[7:0] = AXH, the device expects the

next continuous instruction to be another SDIOR

command, BBH, and does not require the opcode to be

entered again. The host may set the next SDIOR cycle

by driving CE# low, then sending the 2-bit wide input for

address A[23:0],

followed

the

Set

Mode

Configuration bits M[7:0]. After the Set Mode

Configuration bits, the device outputs the data starting

from the specified address location. There are no

restrictions on address location access.

When M[7:0] is any value other than AXH, the device

expects the next instruction initiated to be a command

instruction. To reset/exit the Set Mode configuration,

execute the Reset Quad I/O command, FFH. See

Figure 5-15 for the SPI Dual I/O Read sequence when

M[7:0] = AXH.

Note:

MSB = Most Significant Bit

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