SST26VF040A-80ISLASHMFVAO datasheet(38/73 Pages) MICROCHIP

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DS20006292B-page 38

SST26VF040A

5.34

Deep Power-Down

The Deep Power-Down (DPD) instruction puts the

device in the lowest power consumption mode – the

Deep Power-Down mode. The Deep Power-Down

instruction is ignored during an internal write operation.

While the device is in Deep Power-Down mode, all

instructions will be ignored except for the Release

Deep Power-Down instruction.

Enter Deep Power-Down mode by initiating the Deep

Power-Down (DPD) instruction (B9H) while driving CE#

low. CE# must be driven high before executing the DPD

instruction. After CE# is driven high, it requires a delay

of TDPD before the standby current ISB is reduced to

deep power-down current IDPD. See Table 5-6 for Deep

Power-Down timing. If the device is busy performing an

internal erase or program operation, initiating a Deep

Power-Down instruction will not place the device in

Deep Power-Down mode. See Figures 5-40 and 5-41

for the DPD instruction sequence.

FIGURE 5-40:

DEEP POWER-DOWN (DPD) SEQUENCE – SQI MODE

FIGURE 5-41:

DEEP POWER-DOWN (DPD) SEQUENCE – SPI MODE

TABLE 5-6:

DEEP POWER-DOWN

Symbol

Parameter

Min.

Max.

Units

TDPD

CE# High to Deep Power-Down

—

µs

TSBR

CE# High to Standby Mode

—

µs

Note:

MSN = Most Significant Nibble; LSN = Least Significant Nibble

MODE 3

SCK

SIO[3:0]

CE#

MODE 0

MSN

LSN

TDPD

Standby Mode Deep Power-Down Mode

CE#

SCK

01 2 3 4 5 6 7

High-Impedance

MODE 0

MODE 3

MSB

TDPD

Standby Mode Deep Power-Down Mode

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