5228-DS05-R datasheet(83/100 Pages) BOARDCOM

83 / 100 page

Data Sheet

BCM5228

7/12/04

Broa d c om Co rp o r a t i o n

Document

5228-DS09-405-R

Timing and AC Characteristics

Page 71

Figure 6: RMII Transmit Packet Timing

Table 51: RMII Transmit Timing

Parameter

Symbol

Min

Typ

Max

Unit

REF_CLK cycle time

REF_CLK

–

TXEN, TX_ER, TXD[1:0] setup time to REF_CLK rising

TXEN_SETUP

–

TXEN, TX_ER, TXD[1:0] hold time from REF_CLK rising

TXEN_HOLD

–

± after TXEN assert

TXEN_TDATA

–

TXD to TD

± steady state delay

TXD_TDATA

–

Note: TXD[1:0] shall provide valid data for each REF_CLK period while TX_EN is asserted. As the REF_CLK frequency

is 10 times the data rate in 10MB/s mode, the value on TXD[1:0] shall be valid such that TXD[1:0] can be sampled every

10th cycle, regardless of the starting cycle within the group and yield the correct frame data.

Table 52: RMII Receive Timing

Parameter

Symbol

Min

Typ

Max

Unit

REF_CLK cycle time

REF_CLK

–

RXD[1:0], CRS, DV, RX_ER output delay from REF_CLK rising

–

CRS_DV assert after RD±

RX_CRS_DV

–

124

–

CRS_DV deassert after RD±

RX_CRS_DV

–

164

–

CRS_DV deassert after RD±

, valid EOP

RX_CRS_DV_EOP

–

237

–

Note: As the REF_CLK frequency is 10 times the data rate in 10 Mbps mode, the value on RXD[1:0] is valid such that

RXD[1:0] can be sampled every 10th cycle, regardless of the starting cycle within the group and yield the correct frame

data. The receiver accounts for differences between the local REF_CLK and the recovered clock through use of

sufficient elasticity buffering. The output delay has a load of 25 pf, which accommodates a PCB trace length of over 12

inches.

TXD[1]

TXD[0]

TX_EN

REF_CLK

111

000

Preamble

Data

SFD

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