5228-DS05-R datasheet(22/100 Pages) BOARDCOM

22 / 100 page

BCM5228

Data Sheet

7/12/04

Broa d c om Co rp o r a t i o n

Page 10

Hardware Signal Definition Table

Document

5228-DS09-405-R

D12,E12

D11,E11

D08,E08

E07,D07

N09,M09

N10,M10

N11,M11

N12,M12

171,170

173,174

189,188

191,192

69,68

71,72

87,86

89,90

SD+{1}, SD–{1}

SD+{2}, SD–{2}

SD+{3}, SD–{3}

SD+{4}, SD–{4}

SD+{5}, SD–{5}

SD+{6}, SD–{6}

SD+{7}, SD–{7}

SD+{8}, SD–{8}

IPD

100BASE-FX Signal Detect. Indicates signal

quality status on the fiber-optic link in

100BASE-FX mode. When the signal quality

is good, the SD+ pin should be driven high

relative to the SD

− pin. 100BASE-FX mode is

disabled when both pins are simultaneously

pulled low or left unconnected.

Reduced Media Independent Interface (RMII)

T15

100

REF_CLK

Reference Clock Input. This pin must be

driven with a continuous 50-MHz clock in the

RMII application and a 125-MHz clock in the

SMII application. It provides timing for

CRS_DV, RXD1, RXD0, TX_EN,

TXD1,TXD0, and RX_ER. Accuracy shall be

±50 ppm, with a duty cycle between 35% and

65% inclusive.

C03

B02

B01

A01

T01

R01

P04

P03

208

207

208

207

TX_EN{1:8}

IPD

Transmit Enable. In RMII mode,active high

indicates that the MAC is presenting di-bits on

TXD1,TXD0 for transmission. TX_EN is

asserted synchronously with the first nibble of

the preamble and remains asserted while all

di-bits to be transmitted are presented to the

RMII. TX_EN transitions synchronously with

respect to REF_CLK.

D16

E16

F15

F16

G15

G16

H15

H16

J15

J16

K15

K16

L15

L16

M15

M16

149

150

145

146

139

140

135

136

127

128

123

124

117

118

113

114

149

150

145

146

139

140

135

136

127

128

123

124

117

118

113

114

TXD1{1}

TXD0{1}

TXD1{2}

TXD0{2}

TXD1{3}

TXD0{3}

TXD1{4}

TXD0{4}

TXD1{5}

TXD0{5}

TXD1{6}

TXD0{6}

TXD1{7}

TXD0{7}

TXD1{8}

TXD0{8}

IPD

Transmit Data Input. In RMII mode,

TXD1,TXD0 dibit wide data is input on these

pins for transmission by the PHY. The data is

synchronous with REF_CLK. TXD1 is the

most significant bit. Values other than 00 on

TXD1,TXD0 while TX_EN is deasserted are

ignored by the PHY.

In SMII mode, the TXD0{1:8} form the STXD

pins for each PHY.

Table 2: Pin Definitions (Cont.)

BCM5228B BCM5228F BCM5228U Pin Label

I/O

Description

5228-DS05-R Folha de dados(PDF) 22 Page - Broadcom Corporation.

5228-DS05-R Folha de dados(HTML) 22 Page - Broadcom Corporation.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Folha de dados Download

Ligação URL