5228-DS05-R datasheet(68/100 Pages) BOARDCOM

68 / 100 page

BCM5228

Data Sheet

7/12/04

Broa d c om Co rp o r a t i o n

Page 56

Auxiliary Mode 2 Register

Document

5228-DS09-405-R

INTR Status. Represents status of the INTR# pin. A 1 indicates that the interrupt mask is off and that one or more of the

change bits are set. A register read clears the bit.

AUXILIARY MODE 2 REGISTER

10BASE-T Dribble Bit Correct. When enabled, the PHY rounds-down to the nearest nibble when dribble bits are present

on the 10BASE-T input stream.

Jumbo Packet Enable. When enabled, the 100BASE-X unlock timer changes to allow long packets. See

Table 5 on page 27 for details.

Jumbo Packet FIFO Enable. When enabled, the RMII/SMII/S3MII receive FIFO doubles from 7 nibbles to 14 nibbles. The

Jumbo Packet FIFO Enable bit should be set to a 1 when jumbo packet mode is enabled. See Table 4 on page 27 and

Table 5 on page 27 for details.

Table 35: Auxiliary Mode 2 Register (Address 27d, 1Bh)

BIt

Name

R/W

Description

Default

15:12

Reserveda

a. Preserve existing values of reserved bits by completing a “Read/Modify Write.”

––

10BASE-T Dribble Bit

Correct

R/W

1 = Enable

0 = Disable

Jumbo Packet Enable

R/W

1 = Enable

0 = Disable

Jumbo Packet FIFO Enable

R/W

1 = Enable

0 = Disable

Reserveda

––

Block 10BASE-T Echo

Mode

R/W

1 = Enable

0 = Disable

Traffic Meter LED Mode

R/W

1 = Enable

0 = Disable

Activity LED Force On

R/W

1 = On

0 = Normal operation

Reserveda

––

Reserveda

––

Activity/Link LED Mode

R/W

1 = Enable

0 = Disable

Qual Parallel Detect Mode

R/W

1 = Enable

0 = Disable

Reserveda

––

Note: R/W = Read/Write, RO = Read Only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL and LH Clear

after read operation.

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