5228-DS05-R datasheet(74/100 Pages) BOARDCOM

74 / 100 page

BCM5228

Data Sheet

7/12/04

Broa d c om Co rp o r a t i o n

Page 62

Broadcom Test Register

Document

5228-DS09-405-R

Acknowledge Complete. This read-only bit returns a 1 after the acknowledgment exchange portion of the auto-negotiation

process has been completed and the arbitrator state machine has exited the acknowledge complete state. It remains this

value until the auto-negotiation process is restarted, a link fault occurs, auto-negotiation is disabled, or the BCM5228 is reset.

Acknowledge Detected. This read-only bit is set to 1 when the arbitrator state machine exits the acknowledge detect state.

It remains high until the auto-negotiation process is restarted, or the BCM5228 is reset.

Ability Detect. This read-only bit returns a 1 when the auto-negotiation state machine is in the ability detect state. It enters

this state a specified time period after the auto-negotiation process begins, and exits after the first FLP burst or link pulses

are detected from the link partner. This bit returns a 00 any time the auto-negotiation state machine is not in the ability detect

state.

Super Isolate. Writing a 1 to this bit places the BCM5228 into the super isolate mode. Similar to the isolate mode, all RMII/

SMII/S3MII inputs are ignored, and all RMII/SMII/S3MII outputs are tri-stated. Additionally, all link pulses are suppressed.

This allows the BCM5228 to coexist with another PHY on the same adapter card, with only one being activated at any time.

See also “Super Isolate Mode” on page 26.

10BASE-T Serial Mode. Writing a 1 to bit 1 of the Auxiliary Mode register enables the 10BASE-T Serial mode. In

10BASE-T Serial mode, data packets traverse to the MAC layer across only TXD0 and RXD0 at a rate of 10 MHz. Serial

operation is not available in 100BASE-X mode.

BROADCOM TEST REGISTER

Shadow Register Enable. Writing a 1 to bit 7 of register 1Fh allows R/W access to the shadow registers.

Table 39: Broadcom Test (Address 31d, 1Fh)

BIt

Name

R/W

Description

Default

15:8

Reserveda

a. Preserve existing values of reserved bits by completing a “Read/Modify Write.”

–

–00h

Shadow Register Enable

R/W

1 = Enable shadow registers 1Ah-1Eh

0 = Disable shadow registers

Reserveda

–

–0

Reserveda

–

–0

4:0

Reserveda

–

–0Bh

Note: R/W = Read/Write, RO = Read Only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL and LH Clear

after read operation.

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