5228-DS05-R datasheet(64/100 Pages) BOARDCOM

64 / 100 page

BCM5228

Data Sheet

7/12/04

Broa d c om Co rp o r a t i o n

Page 52

Auxiliary Control/Status Register

Document

5228-DS09-405-R

AUXILIARY CONTROL/STATUS REGISTER

Jabber Disable. 10BASE-T operation only. Bit 15 of the Auxiliary Control register allows the user to disable the jabber detect

function, defined in the IEEE standard. This function shuts off the transmitter when a transmission request has exceeded a

maximum time limit. By writing a 1 to bit 15 of the Auxiliary Control register, the jabber detect function is disabled. Writing a

0 to this bit or resetting the chip restores normal operation. Reading this bit returns the value of Jabber Detect Disable.

Link Disable. Writing a 1 to bit 14 of the Auxiliary Control register allows the user to disable the link integrity state machines,

and place the BCM5228 into forced link pass status. Writing a 0 to this bit or resetting the chip restores the link integrity

functions. Reading this bit returns the value of Link Integrity Disable.

HSQ:LSQ. Extend or decrease the squelch levels for detection of incoming 10BASE-T data packets. The default squelch

levels implemented are those defined in the IEEE standard. The high-squelch and low-squelch levels are useful for situations

where the IEEE-prescribed levels are inadequate. The squelch levels are used by the CRS/LINK block to filter out noise and

recognize only valid packet preambles and link integrity pulses. Extending the squelch levels allows the BCM5228 to operate

properly over longer cable lengths. Decreasing the squelch levels can be useful in situations where there is a high level of

noise present on the cables. Reading these 2 bits returns the value of the squelch levels.

Table 32: Auxiliary Control/Status Register (Address 24d, 18h)

Bit

Name

R/W

Description

Default

Jabber Disable

R/W

1= Jabber function disabled in PHY

0 = Jabber function enabled in PHY

Link Disable

R/W

1= Link Integrity test disabled in PHY

0 = Link Integrity test is enabled in PHY

13:8

Reserveda

a. Preserve existing values of reserved bits by completing a “Read/Modify Write.”

–

000000

7:6

HSQ:LSQ

R/W

These two bits define the squelch mode of the

10BASE-T carrier sense mechanism:

00 = Normal squelch

01 = Low squelch

10 = High squelch

11 = Not allowed

5:4

Edge Rate [1:0]

R/W

00 = 1 ns

01 = 2 ns

10 = 3 ns

11 = 4 ns

Auto-Negotiation Indicator

1 = Auto-negotiation activated

0 = Speed forced manually

Force 100/10 Indication

1 = Speed forced to 100BASE-X

0 = Speed forced to 10BASE-T

Speed Indication

1 = 100BASE-X

0 = 10BASE-T

Full-Duplex Indication

1 = Full-duplex active

0 = Full-duplex not active

Note: R/W = Read/Write, RO = Read Only, SC = Self Clear, LL = Latched Low, LH = Latched High, LL and LH Clear

after read operation.

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