5228-DS05-R datasheet(24/100 Pages) BOARDCOM

24 / 100 page

BCM5228

Data Sheet

7/12/04

Broa d c om Co rp o r a t i o n

Page 12

Hardware Signal Definition Table

Document

5228-DS09-405-R

P15

105

SSYNC

IPD

SMII SYNC. In SMII mode, this pin must be

connected to a free running sync pulse

occurring 1 of every 10 clock cycles. In RMII

mode, this pin is NC (No Connect).

Data and controls are transferred through

TXD0 and RXD0 between respective MAC

and PHY in default SMII mode. If source

synchronous enable, SSMII_EN, is high, then

SSYNC provides sync for TXD0 only and

SMII_RSYNC from the BCM5228 provides

sync for RXD0.

R15

103

SSMII_EN

IPD

SMII Source Synchronous (S3MII) Enable.

Active high. When S3MII is enabled, the

BCM5228 provides a source synchronous

receive clock (SMII_RXC) and a sync

(SMII_RSYNC) for MAC to use. The

BCM5228 uses SMII_TXC along with SSYNC

to receive data from the MAC. Signals

CRS_DV, TXER, TXEN, and RXER are not

used when Source Synchronous mode is

enabled.

R16

106

SMII_RXC

O3S

SMII Source Synchronous Receive Clock.

Optional 125-MHz clock in SMII mode for

MAC use to clock in RXD0.

P16

107

SMII_RSYNC

O3S

SMII Source Synchronous SYNC. In S3MII

mode, this pin provides a source

synchronous SYNC pulse for MAC to use

for RXD0 if Source Synchronous is enabled.

T16

104

SMII_TXC

IPD

SMII Source Synchronous Transmit Clock.

125-MHz clock in SMII mode for BCM5228 to

clock in TXD0 if Source Synchronous is

enabled.

Management Data I/O

J01

MDIO

I/OPU

Management Data I/O. This serial input/

output bit is used to read from and write to the

RMII registers. The data value on the MDIO

pin is valid and latched on the rising edge of

MDC.

K01

MDC

IPD

Management Data Clock. The MDC clock

input must be provided to allow RMII

management functions. Clock frequencies up

to 25 MHz are supported.

G05

H05

H04

J05

J03

PHYAD{4:0}

IPD

PHY Address Selects. These inputs set the

base address for MII management PHY

addresses. Also serve as test control inputs

along with TESTEN to select the NAND-chain

test mode.

Table 2: Pin Definitions (Cont.)

BCM5228B BCM5228F BCM5228U Pin Label

I/O

Description

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