SPC564A70B4 datasheet(31/133 Pages) STMICROELECTRONICS

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SPC564A70B4, SPC564A70L7

Introduction

Doc ID 18078 Rev 4

31/133

The Error Correction Status Module supports a number of miscellaneous control functions

for the platform. The ECSM includes these features:

●

Registers for capturing information on platform memory errors if error-correcting codes

(ECC) are implemented

●

For test purposes, optional registers to specify the generation of double-bit memory

errors are enabled on the SPC564A70.

The sources of the ECC errors are:

●

Flash memory

●

SRAM

●

Peripheral RAM (FlexRay, CAN, eTPU2 parameter RAM)

1.5.23

Peripheral bridge (PBRIDGE)

The PBRIDGE implements the following features:

●

Duplicated periphery

●

Master access privilege level per peripheral (per master: read access enable; write

access enable)

●

Write buffering for peripherals

●

Checker applied on PBRIDGE output toward periphery

●

Byte endianess swap capability

1.5.24

Calibration bus interface

The calibration bus interface controls data transfer across the crossbar switch to/from

memories or peripherals attached to the calibration tool connector in the calibration address

space. The calibration bus interface is only available in the calibration tool.

Features include:

●

3.3 V ± 10% I/O (3.0 V to 3.6 V)

●

Memory controller supports various memory types

●

16-bit data bus, up to 22-bit address bus

●

Pin muxing supports 32-bit muxed bus

●

Selectable drive strength

●

Configurable bus speed modes

●

Bus monitor

●

Configurable wait states

1.5.25

Power management controller (PMC)

The PMC contains circuitry to generate the internal 3.3 V supply and to control the

regulation of 1.2 V supply with an external NPN ballast transistor. It also contains low

voltage inhibit (LVI) and power-on reset (POR) circuits for the 1.2 V supply, the 3.3 V supply,

the 3.3 V/5 V supply of the closest I/O segment (VDDEH1), and the 5 V supply of the

regulators (VDDREG).

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