SPC564A70B4 datasheet(30/133 Pages) STMICROELECTRONICS

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Introduction

SPC564A70B4, SPC564A70L7

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Doc ID 18078 Rev 4

comparators. These comparators produce a CPU interrupt when the timer exceeds the

programmed value.

The following features are implemented in the STM:

●

One 32-bit up counter with 8-bit prescaler

●

Four 32-bit compare channels

●

Independent interrupt source for each channel

●

Counter can be stopped in debug mode

1.5.20

Software watchdog timer (SWT)

The SWT is a second watchdog module to complement the standard Power Architecture

watchdog integrated in the CPU core. The SWT is a 32-bit modulus counter, clocked by the

system clock or the crystal clock, that can provide a system reset or interrupt request when

the correct software key is not written within the required time window.

The following features are implemented:

●

32-bit modulus counter

●

Clocked by system clock or crystal clock

●

Optional programmable watchdog window mode

●

Can optionally cause system reset or interrupt request on timeout

●

Reset by writing a software key to memory mapped register

●

Enabled out of reset

●

Configuration is protected by a software key or a write-once register

1.5.21

Cyclic redundancy check (CRC) module

The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The

CRC module features:

●

Support for CRC-16-CCITT (x25 protocol):

–

x16 + x12 + x5 + 1

●

Support for CRC-32 (Ethernet protocol):

–

x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1

●

Zero wait states for each write/read operations to the CRC_CFG and CRC_INP

registers at the maximum frequency

1.5.22

Error correction status module (ECSM)

The ECSM provides a myriad of miscellaneous control functions regarding program-visible

information about the platform configuration and revision levels, a reset status register, a

software watchdog timer, wakeup control for exiting sleep modes, and information on

platform memory errors reported by error-correcting codes and/or generic access error

information for certain processor cores.

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