CC1150-RTR1 datasheet(20/67 Pages) TI

20 / 67 page

CC1150

SWRS037A

Page 20 of 60

contains the number of bytes free for writing

into

the

FIFO.

When

FIFO_BYTES_AVAILABLE=15

, 15 or more

bytes are free. Table 16 gives a status byte

summary.

Bits

Name

Description

CHIP_RDYn

Stays high until power and crystal have stabilized. Should always be low when using

the SPI interface.

6:4

STATE[2:0]

Indicates the current main state machine mode

Value

State

Description

000

Idle

IDLE state

(Also reported for some transitional states instead

of SETTLING or CALIBRATE, due to a small error)

001

Not used

010

Transmit mode

011

FSTXON

Fast TX ready

100

CALIBRATE

Frequency synthesizer calibration is running

101

SETTLING

PLL is settling

110

Not used

111

TXFIFO_UNDERFLOW

TX FIFO has underflowed. Acknowledge with

SFTX

3:0

FIFO_BYTES_AVAILABLE[3:0]

The number of free bytes in the TX FIFO.

Table 16: Status Byte Summary

10.2

The configuration registers on the

CC1150 are

located on SPI addresses from 0x00 to 0x2E.

Table 26 on page 43 lists all configuration

registers. The detailed description of each

page 45.

All configuration registers can be both written

and read. The read/write bit controls if the

writing to registers, the status byte is sent on

the SO pin each time a header byte or data

byte is transmitted on the SI pin. When

reading from registers, the status byte is sent

on the SO pin each time a header byte is

transmitted on the SI pin.

Registers with consecutive addresses can be

accessed in an efficient way by setting the

burst bit in the address header. The address

sets the start address in an internal address

counter. This counter is incremented by one

each new byte (every 8 clock pulses). The

burst access is either a read or a write access

and must be terminated by setting CSn high.

For register addresses in the range 0x30-

0x3D, the burst bit is used to select between

status registers (burst bit is 1) and command

strobes (burst bit is 0). See more in section

10.3 below. Because of this, burst access is

not available for status registers, so they must

be read one at a time. The status registers can

only be read.

10.3

SPI Read

When reading register fields over the SPI

interface while the register fields are updated

by the radio hardware (e.g. MARCSTATE or

TXBYTES), there is a small, but finite,

probability that a single read from the register

is being corrupt. As an example, the probability

of any single read from TXBYTES being

corrupt, assuming the maximum data rate is

used, is approximately 80 ppm. Refer to the

CC1150 Errata Notes [8] for more details.

10.4

Command Strobes

Command Strobes may be viewed as single

byte instructions to

CC1150. By addressing a

Command Strobe register, internal sequences

will be started. These commands are used to

disable the crystal oscillator, enable transmit

mode, flush the TX FIFO etc. The nine

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