OPTION_REG datasheet(114/222 Pages) MICROCHIP

114 / 222 page

MCP19111

DS22331A-page 114

 2013 Microchip Technology Inc.

19.3

PORTGPB and TRISGPB

Registers

PORTGPB is an 8-bit wide, bidirectional port consisting

of seven general purpose I/O ports. The corresponding

data direction register is TRISGPB (Register 19-7).

Setting a TRISGPB bit (= 1) will make the corresponding

PORTGPB pin an input (i.e., disable the output driver).

Clearing

TRISGPB

bit

(= 0)

will

make

the

corresponding PORTGPB pin an output (i.e., enable the

output driver). Example 19-1 shows how to initialize an

I/O port.

Some pins for PORTGPB are multiplexed with an

alternate function for the peripheral, or a clock function.

In general, when a peripheral or clock function is

enabled, that pin may not be used as a general purpose

I/O pin.

Reading the PORTGPB register (Register 19-6) reads

the status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations.

The TRISGPB register (Register 19-7) controls the

PORTGPB pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits in

the TRISGPB register are maintained set when using

them as analog inputs. I/O pins configured as analog

input always read ‘0’. If the pin is configured for a digital

output (either port or alternate function), the TRISGPB bit

must be cleared in order for the pin to drive the signal and

a read will reflect the state of the pin.

19.3.1

INTERRUPT-ON-CHANGE

Each PORTGPA pin is individually configurable as an

interrupt-on-change pin. Control bits IOCB<7:4> and

IOCB<2:0> enable or disable the interrupt function for

each pin. The interrupt-on-change feature is disabled

Power-on

Reset.

Reference

Section 20.0

“Interrupt-On-Change” for more information.

19.3.2

WEAK PULL-UPS

Each of the PORTGPB pins has an individually

configurable

internal

weak

pull-up.

Control

bits

WPUB<7:4> and WPUB<2:1> enable or disable each

pull-up (see Register 19-8). Each weak pull-up is

automatically turned off when the port pin is configured

as an output. All pull-ups are disabled on a Power-on

Reset by the RAPU bit of the OPTION register.

19.3.3

ANSELB REGISTER

The ANSELB register (Register 19-9) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELB bit high will cause all

digital reads on the pin to be read as ‘0’ and allows

analog functions on the pin to operate correctly.

The state of the ANSELB bits has no effect on the digital

output functions. A pin with TRISGPB clear and

ANSELB set will still operate as a digital output, but the

Input mode will be analog. This can cause unexpected

behavior when executing read-modify-write instructions

on the affected port.

The TRISGPB register (Register 19-7) controls the

PORTGPB pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits in

the TRISGPB register are maintained set when using

them as analog inputs. I/O pins configured as analog

input always read ‘0’.

19.3.4

PORTGPB FUNCTIONS AND

OUTPUT PRIORITIES

Each PORTGPB pin is multiplexed with other functions.

The pins, their combined functions and their output

priorities are shown in Table 19-3. For additional

information, refer to the appropriate section in this data

sheet.

PORTGPB pin GPB0 is a true open drain pin with no

connection back to VDD.

When multiple outputs are enabled, the actual pin

control goes to the peripheral with the highest priority.

Analog input functions, such as ADC, and some digital

input functions are not included in the list below. These

inputs are active when the I/O pin is set for Analog

mode using the ANSELB registers. Digital output

functions may control the pin when it is in Analog mode,

with the priority shown in Table 19-3.

Note:

The ANSELB bits default to the Analog

mode after Reset. To use any pins as

digital general purpose or peripheral

inputs, the corresponding ANSELB bits

must be initialized to ‘0’ by the user’s

software.

TABLE 19-3:

PORTGPB OUTPUT PRIORITY

Pin Name

Function Priority(1)

GPB0

GPB0 (open drain input/output)

SDA

GPB1

AN4

EAPIN

GPB2

AN5

GPB4

AN6

ICSPDAT

ICDDAT

GPB5

AN7

ICSPCLK

ICDCLK

ALT_CLKPIN

GPB6

GPB7

Note

Priority listed from highest to lowest.

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