TMS320DM647 datasheet(14/181 Pages) TI

14 / 181 page

TMS320DM647

TMS320DM648

SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009

www.ti.com

Table 2-3. Memory Map Summary (continued)

START

END

SIZE

C64x+

ADDRESS

(Bytes)

MEMORY MAP

0x02C8 0000

0x02CB FFFF

256K

Reserved

0x02CC 0000

0x02CF FFFF

256K

Reserved

0x02D0 0000

0x02D0 1FFF

Ethernet Subsystem CPPI RAM(1)

0x02D0 2000

0x02D0 2FFF

Ethernet Subsystem Control

0x02D0 3000

0x02D0 3FFF

Ethernet Subsystem 3PSW

0x02D0 4000

0x02D0 47FF

Ethernet Subsystem MDIO

0x02D0 4800

0x02D0 4BFF

Ethernet Subsystem SGMII0

0x02D0 4C00

0x02D0 4FFF

Ethernet Subsystem SGMII1 (DM648 only)

0x02D0 5000

0x02D0 57FF

Reserved

0x02D0 5800

0x02DB FFFF

746K

Reserved

0x02DC 0000

0x02DF FFFF

256K

Reserved

0x02E0 0000

0x02E0 3FFF

16K

Reserved

0x02E0 4000

0x02FF FFFF

2M – 16K

Reserved

0x0300 0000

0x03FF FFFF

16M

Reserved

0x0400 0000

0x0FFF FFFF

192M

Reserved

0x1000 0000

0x1FFF FFFF

256M

Reserved

0x2000 0000

0x2FFF FFFF

256M

Reserved

0x3000 0000

0x3000 00FF

256

Reserved

0x3000 0100

0x33FF FFFF

64M – 256

Reserved

0x3400 0000

0x3400 00FF

256

Reserved

0x3400 0100

0x37FF FFFF

64M – 256

Reserved

0x3800 0000

0x3BFF FFFF

64M

VLYNQ

0x3C00 0000

0x3CFF FFFF

16M

Reserved

0x3D00 0000

0x3DFF FFFF

16M

Reserved

0x3E00 0000

0x3FFF FFFF

32M

Reserved

0x4000 0000

0x4FFF FFFF

256M

PCI Data

0x5000 0000

0x51FF FFFF

32M

VP0 ChannelA Data

0x5200 0000

0x53FF FFFF

32M

VP0 ChannelB Data

0x5400 0000

0x55FF FFFF

32M

VP1 ChannelA Data

0x5600 0000

0x57FF FFFF

32M

VP1 ChannelB Data

0x5800 0000

0x59FF FFFF

32M

VP2 ChannelA Data

0x5A00 0000

0x5BFF FFFF

32M

VP2 ChannelB Data

0x5C00 0000

0x5DFF FFFF

32M

Reserved

0x5E00 0000

0x5FFF FFFF

32M

Reserved

0x6000 0000

0x61FF FFFF

32M

VP3 ChannelA Data

0x6200 0000

0x63FF FFFF

32M

VP3 ChannelB Data

0x6400 0000

0x65FF FFFF

32M

VP4 ChannelA Data

0x6600 0000

0x67FF FFFF

32M

VP4 ChannelB Data

0x6800 0000

0x6FFF FFFF

128M

Reserved

0x7000 0000

0x77FF FFFF

128M

EMIFA Configuration

0x7800 0000

0x7FFF FFFF

128M

DDR2 EMIF Configuration

0x8000 0000

0x8FFF FFFF

256M

Reserved

0x9000 0000

0x9FFF FFFF

256M

Reserved

0xA000 0000

0xA3FF FFFF

64M

EMIFA CE2(2)

0xA400 0000

0xAFFF FFFF

256 - 64M

Reserved

0xB000 0000

0xB3FF FFFF

64M

EMIFA CE3(2)

(1)

The 8K CPPI Descriptor memory is mapped to an address range 0x02C8 2000 - 0x02C8 3FFF, from the perspective of the Ethernet

subsystem 3PSW. The buffer descriptors, when accessed from the C64x+, are addressed from 0x02D0 0000. However, within these

buffer descriptors, when the pointer to the next buffer descriptor is programmed, the Ethernet subsystem 3PSW is interpreting this value.

Thus, this programmed value should be in the address range starting from 0x02C8 2000.

(2)

The EMIFA CS0 and CS1 are not functionally supported; therefore, they are not pinned out.

Device Overview

Submit Documentation Feedback

Product Folder Link(s): TMS320DM647 TMS320DM648

TMS320DM647 Folha de dados(PDF) 14 Page - Texas Instruments

TMS320DM647 Folha de dados(HTML) 14 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL