TMS320DM647 datasheet(99/181 Pages) TI

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TMS320DM647

TMS320DM648

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SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009

NOTE

The region (see Figure 6-14) should encompass all DDR2 circuitry and varies depending

on placement. Non-DDR2 signals should not be routed on the DDR signal layers within

the DDR2 keep out region. Non-DDR2 signals may be routed in the region provided they

are routed on layers separated from DDR2 signal layers by a ground layer. No breaks

should be allowed in the reference ground layers in this region. In addition, the 1.8-V

power plane should cover the entire keep out region.

6.9.3.6

Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.

Table 6-32 contains the minimum numbers and capacitance required for the bulk bypass capacitors. This

table covers only the bypass needs of the DSP and DDR2 interfaces. Additional bulk bypass capacitance

may be needed for other circuitry.

Table 6-32. Bulk Bypass Capacitors

NO.

PARAMETER

MIN

MAX

UNIT

DVDD18 Bulk Bypass Capacitor Count

(1)

Devices

DVDD18 Bulk Bypass Total Capacitance

DDR#1 Bulk Bypass Capacitor Count(1)

Devices

DDR#1 Bulk Bypass Total Capacitance

DDR#2 Bulk Bypass Capacitor Count(1) (2)

Devices

DDR#2 Bulk Bypass Total Capacitance(2)

(1)

These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed

(HS) bypass caps.

(2)

Only used on 32-bit wide DDR2 memory systems

6.9.3.7

High-Speed Bypass Capacitors

High-Speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly

important to minimize the parasitic series inductance of the HS bypass cap, DSP/DDR power, and

DSP/DDR ground connections. Table 6-33 contains the specification for the HS bypass capacitors as well

as for the power connections on the PCB.

6.9.3.8

Net Classes

Table 6-34 lists the clock net classes for the DDR2 interface. Table 6-35 lists the signal net classes, and

associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the

termination and routing rules that follow.

Table 6-33. High-Speed Bypass Capacitors

NO.

PARAMETER

MIN

MAX

UNIT

HS Bypass Capacitor Package Size(1)

0402

10 Mils

Distance from HS bypass capacitor to device being bypassed

250

Mils

Number of connection vias for each HS bypass capacitor(2)

Vias

Trace length from bypass capacitor contact to connection via

Mils

Number of connection vias for each DDR2 device power or ground balls

Vias

Trace length from DDR2 device power ball to connection via

Mils

DVDD18 HS Bypass Capacitor Count

(3)

Devices

DVDD18 HS Bypass Capacitor Total Capacitance

1.2

DDR#1 HS Bypass Capacitor Count(3)

Devices

(1)

L × W, 10 mil units ( i.e., a 0402 is a 40 × 20 mil surface mount capacitor)

(2)

An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.

(3)

These devices should be placed as close as possible to the device being bypassed.

Peripheral Information and Electrical Specifications

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