TMS320DM647 datasheet(57/181 Pages) TI

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Transmission Line

4.0 pF

1.85 pF

Z0 = 50

Ω

(see Note)

Tester Pin Electronics

Data Sheet Timing Reference Point

Output

Under

Test

NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must

be taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission

line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

Ω

3.5 nH

Device Pin

(see Note)

ref

Vref = VIL MAX (or VOL MAX)

Vref = VIH MIN (or VOH MIN)

TMS320DM647

TMS320DM648

www.ti.com

SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009

Peripheral Information and Electrical Specifications

6.1

Parameter Information

Figure 6-1. Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of ac timing signals. This

load capacitance value does not indicate the maximum load the device is capable of driving.

6.1.1

3.3-V Signal Transition Levels

All input and output timing parameters are referenced to Vref for both 0 and 1 logic levels. For 3.3-V I/O,

Vref = 1.5 V. For 1.8-V I/O, Vref = 0.9 V.

Figure 6-2. Input and Output Voltage Reference Levels for ac Timing Measurements

All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,

VOLMAX and VOH MIN for output clocks.

Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels

6.1.2

3.3-V Signal Transition Rates

All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).

Peripheral Information and Electrical Specifications

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