TMS320DM647 datasheet(65/181 Pages) TI

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DIVIDERD4

CLKIN1

PLLEN(PLLCTL.[0])

SYSCLK1

SYSCLK2

AECLKIN(ExternalEMIFClockInput)

EMIFA

DIVIDERPREDIV

DIVIDERD1

DIVIDERD2

AECLKOUT

PLLV1

EMIFilter

+1.8V

560pF 0.1 F

SYSCLK5

SYSREFCLK

(C64x+MegaModule)

DIVIDERD5

PLL1Controller

(EMIFInputClock)

/1,/2,/3

ENA

PREDEN(PREDIV.[15])

ENA

/4.../8

PLL1

D4EN(PLLDIV4.[15])

SYSCLK4

(Internal

EMIFClock

Input)

SYSCLK5

SYSCLK3

DIVIDERD3

SYSCLK6

DIVIDERD6

ENA

D2EN(PLLDIV2.[15])

/1,/2,

...,/8

(EmulationandTrace)

VICP cop_clk/2

VICP cop_clk

AECLKINSEL

(AEA[17]pin)

VCLK

VLYNQ

CLKDIR

(CTRL.[15])

/1,/2,

...,/8

CLKDIV

(CTRL.[18:16])

PLLM

x1,

x16tox32

TMS320DM647

TMS320DM648

www.ti.com

SPRS372F – JANUARY 2010 – REVISED SEPTEMBER 2009

6.4

PLL1 Controller

The primary PLL controller generates the input clock to the C64x+ megamodule (including the CPU) as

well as most of the system peripherals such as the multichannel audio serial ports (McASPs) and the

external memory interface (EMIFA). Figure 6-5 shows a functional block diagram of the PLL Input Clock.

Figure 6-5. PLL Input Clock

As shown in Figure 6-5, the PLL1 controller features a software-programmable PLL multiplier controller

(PLLM) and seven dividers (PREDIV, D1, D2, D3, D4, D5). The PLL1 controller uses the device input

Peripheral Information and Electrical Specifications

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