HD64F2149YV datasheet(673/1075 Pages) RENESAS

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Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 645 of 1044

REJ09B0280-0300

18B.3.5 Host Interface Serialized Interrupt Operation (SERIRQ)

A host interrupt request can be issued from the host interface by means of the SERIRQ pin. In a

host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the

serialized interrupt transfer cycle generated by the host or a supporting function, and a request

signal is generated by the frame corresponding to that interrupt. The timing is shown in figure

18B.6.

IRQ1

Host controller

None

SERIRQ

Drive source

LCLK

START

Start frame

IRQ0 frame

IRQ1 frame

IRQ2 frame

IRQ15

Host controller

None

SERIRQ

Driver

LCLK

START

STOP

IOCHCK frame

Stop frame

Next cycle

IRQ14 frame

IRQ15 frame

H = Host control, SL = Slave control, R = Recovery, T = Turnaround, S = Sample

H = Host control, R = Recovery, T = Turnaround, S = Sample, I = Idle

Figure 18B.6 SERIRQ Timing

The serialized interrupt transfer cycle frame configuration is as follows. Two of the states

comprising each frame are the recover state in which the SERIRQ signal is returned to the 1-level

at the end of the frame, and the turnaround state in which the SERIRQ signal is not driven. The

recover state must be driven by the host or slave processor that was driving the preceding state.

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