HD64F2149YV datasheet(669/1075 Pages) RENESAS

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Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 641 of 1044

REJ09B0280-0300

18B.3.4 Host Interface Shutdown Function (LPCPD)

The host interface can be placed in the shutdown state according to the state of the

LPCPD pin.

There are two kinds of host interface shutdown state: LPC hardware shutdown and LPC software

shutdown. The LPC hardware shutdown state is controlled by the

LPCPD pin, while the software

shutdown state is controlled by the SDWNB bit. In both states, the host interface enters the reset

state by itself, and is no longer affected by external signals other than the

LRESET and LPCPD

signals.

Placing the slave processor in sleep mode or software standby mode is effective in reducing

current dissipation in the shutdown state. If software standby mode is set, some means must be

provided for exiting software standby mode before clearing the shutdown state with the

LPCPD

signal.

If the SDWNE bit has been set to 1 beforehand, the LPC hardware shutdown state is entered at the

same time as the

LPCPD signal falls, and prior preparation is not possible. If the LPC software

shutdown state is set by means of the SDWNB bit, on the other hand, the LPC software shutdown

state cannot be cleared at the same time as the rise of the

LPCPD signal. Taking these points into

consideration, the following operating procedure uses a combination of LPC software shutdown

and LPC hardware shutdown.

1. Clear the SDWNE bit to 0.

2. Set the ERRIE bit to 1 and wait for an interrupt by the SDWN flag.

3. When an ERRI interrupt is generated by the SDWN flag, check the host interface internal

status flags and perform any necessary processing.

4. Set the SDWNB bit to 1 to set LPC software standby mode.

5. Set the SDWNE bit to 1 and make a transition to LPC hardware standby mode. The SDWNB

bit is cleared automatically.

6. Check the state of the

LPCPD signal to make sure that the LPCPD signal has not risen during

steps 3 to 5. If the signal has risen, clear SDWNE to 0 to return to the state in step 1.

7. Place the slave processor in sleep mode or software standby mode as necessary.

8'. If software standby mode has been set, exit software standby mode by some means

independent of the LPC.

8. When a rising edge is detected in the

LPCPD signal, the SDWNE bit is automatically cleared

to 0. If the slave processor has been placed in sleep mode, the mode is exited by means of

LRESET signal input, on completion of the LPC transfer cycle, or by some other means.

Table 18B.5 shows the scope of HIF pin shutdown

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