HD64F2149YV datasheet(670/1075 Pages) RENESAS

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Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 642 of 1044

REJ09B0280-0300

Table 18B.5 Scope of HIF Pin Shutdown

Abbreviation

Port

Scope of

Shutdown

I/O

Notes

LAD3 to LAD0

P33–P30

I/O

Hi-Z

LFRAME

P34

Input

Hi-Z

LRESET

P35

Input

LPC hardware reset function is active

LCLK

P36

Input

Hi-Z

SERIRQ

P37

I/O

Hi-Z

LSCI

PB1

∆

I/O

Hi-Z, only when LSCIE = 1

LSMI

PB0

∆

I/O

Hi-Z, only when LSMIE = 1

PME

P80

∆

I/O

Hi-Z, only when PMEE = 1

GA20

P81

∆

I/O

Hi-Z, only when FGA20E = 1

CLKRUN

P82

I/O

Hi-Z

LPCPD

P83

Input

Needed to clear shutdown state

Legend:

O: Pins shut down by the shutdown function

∆: Pins shut down only when the HIF (LPC) function is selected by register setting

X: Pins not shut down

In the LPC shutdown state, the LPC’s internal state and some register bits are initialized. The

order of priority of LPC shutdown and reset states is as follows.

1. System reset (reset by

STBY or RES pin input, or WDT0 overflow)

•

All register bits, including bits LPC3E to LPC1E, are initialized.

2. LPC hardware reset (reset by

LRESET pin input)

•

LRSTB, SDWNE, and SDWNB bits are cleared to 0.

3. LPC software reset (reset by LRSTB)

•

SDWNE and SDWNB bits are cleared to 0.

4. LPC hardware shutdown

•

SDWNB bit is cleared to 0.

5. LPC software shutdown

The scope of the initialization in each mode is shown in table 18B.6.

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