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HD64F2149YV Folha de dados(PDF) 606 Page - Renesas Technology Corp |
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HD64F2149YV Folha de dados(HTML) 606 Page - Renesas Technology Corp |
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606 / 1075 page ![]() Section 17 Keyboard Buffer Controller Rev. 3.00 Jan 18, 2006 page 578 of 1044 REJ09B0280-0300 17.3.7 Receive Timing Figure 17.12 shows the receive timing. N + 1 N + 2 N KCLK (pin) Note: * The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. KD (pin) Internal KCLK (KCLKI) Falling edge signal RXCR3 to RXCR0 Internal KD (KDI) KBBR7 to KBBR0 φ* Figure 17.12 Receive Counter and KBBR Data Load Timing |
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