HD64F2149YV datasheet(576/1075 Pages) RENESAS

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Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 548 of 1044

REJ09B0280-0300

• Note on ICDR Read at End of Master Reception

To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1

and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is

high, and generates the stop condition. After this, receive data can be read by means of an

ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to

ICDR, and so it will not be possible to read the second byte of data.

If it is necessary to read the second byte of data, issue the stop condition in master receive

mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the

BBSY bit in the ICCR register is cleared to 0, the stop condition has been generated, and the

bus has been released, then read the ICDR register with TRS cleared to 0.

Note that if the receive data (ICDR data) is read in the interval between execution of the

instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the

actual generation of the stop condition, the clock may not be output correctly in subsequent

master transmission.

Clearing of the MST bit after completion of master transmission/reception, or other

modifications of IIC control bits to change the transmit/receive operating mode or settings,

must be carried out during interval (a) in figure 16.17 (after confirming that the BBSY bit has

been cleared to 0 in the ICCR register).

SDA

SCL

Internal clock

BBSY bit

Master receive mode

ICDR reading

prohibited

Bit 0

Stop condition

(a)

Start condition

Execution of stop

condition issuance

instruction

(0 written to BBSY

and SCP)

Confirmation of stop

condition generation

(0 read from BBSY)

Start condition

issuance

Figure 16.18 Points for Attention Concerning Reading of Master Receive Data

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