HD64F2149YV datasheet(575/1075 Pages) RENESAS

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Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 547 of 1044

REJ09B0280-0300

Table 16.8

2C Bus Timing (with Maximum Influence of t

Sr/tSf)

Time Indication (at Maximum Transfer Rate) [ns]

Item

cyc

Indication

Sr/tSf

Influence

(Max.)

2C Bus

Specification

(Min.)

φφφφ =

5 MHz

φφφφ =

8 MHz

φφφφ =

10 MHz

Standard mode

–1000

4000

SCLHO

0.5t

SCLO

(–t

Sr)

High-speed mode –300

600

950

Standard mode

–250

4700

4750

SCLLO

0.5t

SCLO

(–t

Sf )

High-speed mode –250

1300

1000*

Standard mode

–1000

4700

3800*

3875*

3900*

BUFO

0.5t

SCLO –

cyc ( –tSr )

High-speed mode –300

1300

750*

825*

850*

Standard mode

–250

4000

4550

4625

4650

STAHO

0.5t

SCLO –

cyc (–tSf )

High-speed mode –250

600

800

875

900

Standard mode

–1000

4700

9000

STASO

SCLO

(–t

Sr )

High-speed mode –300

600

2200

Standard mode

–1000

4000

4400

4250

4200

STOSO

0.5t

SCLO +

cyc (–tSr )

High-speed mode –300

600

1350

1200

1150

Standard mode

–1000

250

3100

3325

3400

SDASO

(master)

SCLLO*

3 –

cyc (–tSr )

High-speed mode –300

100

400

625

700

Standard mode

–1000

250

1300

2200

2500

SDASO

(slave)

SCLL

*3 –

12t

cyc

(–t

Sr )

High-speed mode –300

100

–1400*

–500*

–200*

Standard mode

600

375

300

SDAHO

cyc

High-speed mode 0

600

375

300

Notes: The maximum operating frequency for the H8S/2169 and H8S/2149 is 10 MHz.

1. Does not meet the I

2C bus interface specification. Remedial action such as the following

is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and

fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;

(d) select slave devices whose input timing permits this output timing.

The values in the above table will vary depending on the settings of the IICX bit and bits

CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the

maximum transfer rate; therefore, whether or not the I

2C bus interface specifications are

met must be determined in accordance with the actual setting conditions.

2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (t

SCLL –

cyc).

3. Calculated using the I

2C bus specification values (standard mode: 4700 ns min.; high-

speed mode: 1300 ns min.).

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