HD64F2149YV datasheet(573/1075 Pages) RENESAS

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Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 545 of 1044

REJ09B0280-0300

16.4

Usage Notes

• In master mode, if an instruction to generate a start condition is immediately followed by an

instruction to generate a stop condition, neither condition will be output correctly. To output

consecutive start and stop conditions, after issuing the instruction that generates the start

condition, read the relevant ports, check that SCL and SDA are both low, then issue the

instruction that generates the stop condition. Note that SCL may not yet have gone low when

BBSY is cleared to 0.

• Either of the following two conditions will start the next transfer. Pay attention to these

conditions when reading or writing to ICDR.

 Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from

ICDRT to ICDRS)

 Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from

ICDRS to ICDRR)

• Table 16.6 shows the timing of SCL and SDA output in synchronization with the internal

clock. Timings on the bus are determined by the rise and fall times of signals affected by the

bus load capacitance, series resistance, and parallel resistance.

Table 16.6

2C Bus Timing (SCL and SDA Output)

Item

Symbol

Output Timing

Unit

Notes

SCL output cycle time

SCLO

28t

cyc to 256tcyc

SCL output high pulse width

SCLHO

0.5t

SCLO

SCL output low pulse width

SCLLO

0.5t

SCLO

Figure 25.27

(reference)

SDA output bus free time

BUFO

0.5t

SCLO – 1tcyc

Start condition output hold time

STAHO

0.5t

SCLO – 1tcyc

Retransmission start condition output

setup time

STASO

SCLO

Stop condition output setup time

STOSO

0.5t

SCLO + 2tcyc

Data output setup time (master)

SDASO

SCLLO – 3tcyc

Data output setup time (slave)

SCLL – (6tcyc or

12t

cyc*)

Data output hold time

SDAHO

cyc

Note:

cyc when IICX is 0, 12tcyc when 1.

• SCL and SDA input is sampled in synchronization with the internal clock. The AC timing

therefore depends on the system clock cycle t

cyc, as shown in I

2C bus Timing in section 25,

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