HD64F2149YV datasheet(574/1075 Pages) RENESAS

574 / 1075 page

Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 546 of 1044

REJ09B0280-0300

Electrical Characteristics. Note that the I

2C bus interface AC timing specifications will not be

met with a system clock frequency of less than 5 MHz.

• The I2C bus interface specification for the SCL rise time t

sr is under 1000 ns (300 ns for high-

speed mode). In master mode, the I

2C bus interface monitors the SCL line and synchronizes

one bit at a time during communication. If t

sr (the time for SCL to go from low to VIH) exceeds

the time determined by the input clock of the I

2C bus interface, the high period of SCL is

extended. The SCL rise time is determined by the pull-up resistance and load capacitance of

the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance

and load capacitance so that the SCL rise time does not exceed the values given in the table

below.

Table 16.7

Permissible SCL Rise Time (t

SR) Values

Time Indication

IICX

cyc

Indication

2C Bus

Specification (Max.)

φφφφ =

5 MHz

φφφφ =

8 MHz

φφφφ =

10 MHz

07.5t

cyc

Normal mode

1000 ns

937 ns

750 ns

High-speed mode

300 ns

17.5t

cyc

Normal mode

1000 ns

High-speed mode

300 ns

Note:

The maximum operating frequency for the H8S/2169 and H8S/2149 is 10 MHz.

• The I2C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns

and 300 ns. The I

2C bus interface SCL and SDA output timing is prescribed by t

cyc, as shown in

table 16.6. However, because of the rise and fall times, the I

2C bus interface specifications may

not be satisfied at the maximum transfer rate. Table 16.8 shows output timing calculations for

different operating frequencies, including the worst-case influence of rise and fall times.

BUFO fails to meet the I

2C bus interface specifications at any frequency. The solution is either (a)

to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a

stop condition and issuance of a start condition, or (b) to select devices whose input timing

permits this output timing for use as slave devices connected to the I

2C bus.

SCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I

2C bus interface

specifications for worst-case calculations of t

Sr/tSf. Possible solutions that should be investigated

include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load,

(b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input

timing permits this output timing for use as slave devices connected to the I

2C bus.

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