HD64F2149YV datasheet(444/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Section 14 Watchdog Timer (WDT)

Rev. 3.00 Jan 18, 2006 page 416 of 1044

REJ09B0280-0300

• WDT1 input clock selection

Bit 4

Bit 2

Bit 1

Bit 0

Description

PSS

CKS2

CKS1

CKS0

Clock

Overflow Period* (when

φφφφ = 10 MHz

and

φφφφ

SUB = 32.768 kHz)

φ/2 (Initial value) 51.2 µs

φ/64

1.6 ms

φ/128

3.2 ms

φ/512

13.1 ms

φ/2048

52.4 ms

φ/8192

209.7 ms

φ/32768

838.9 ms

φ/131072

3.36 s

SUB/2

15.6 ms

SUB/4

31.3 ms

SUB/8

62.5 ms

SUB/16

125 ms

SUB/32

250 ms

SUB/64

500 ms

SUB/128

1 s

SUB/256

2 s

Note:

The overflow period is the time from when TCNT starts counting up from H'00 until

overflow occurs.

14.2.3

System Control Register (SYSCR)

CS2E

R/W

IOSE

R/W

INTM1

INTM0

R/W

XRST

RAME

R/W

NMIEG

R/W

HIE

R/W

Bit

Initial value

Read/Write

Only bit 3 is described here. For details on functions not related to the watchdog timer, see

sections 3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant

modules.

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