HD64F2149YV datasheet(441/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

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Fabricante Electrônico	RENESAS [Renesas Technology Corp]

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Section 14 Watchdog Timer (WDT)

Rev. 3.00 Jan 18, 2006 page 413 of 1044

REJ09B0280-0300

TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared

to 0. It is not initialized in software standby mode.

Note: *

TCNT is write-protected by a password to prevent accidental overwriting. For details

see section 14.2.4, Notes on Register Access.

14.2.2

Timer Control/Status Register (TCSR)

• TCSR0

OVF

R/(W)*

WT/

R/W

TME

R/W

RSTS

R/W

RST/

NMI

R/W

CKS0

R/W

CKS2

R/W

CKS1

R/W

Bit

Initial value

Read/Write

Note: * Only 0 can be written, to clear the flag.

• TCSR1

Bit

Initial value

Read/Write

Note: * Only 0 can be written, to clear the flag.

OVF

R/(W)*

WT/

R/W

TME

R/W

PSS

R/W

RST/

NMI

R/W

CKS0

R/W

CKS2

R/W

CKS1

R/W

TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be

input to TCNT, and the timer mode.

TCSR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Note: *

TCSR is write-protected by a password to prevent accidental overwriting. For details

see section 14.2.4, Notes on Register Access.

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