HD64F2149YV datasheet(442/1075 Pages) RENESAS

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Section 14 Watchdog Timer (WDT)

Rev. 3.00 Jan 18, 2006 page 414 of 1044

REJ09B0280-0300

Bit 7—Overflow Flag (OVF): A status flag that indicates that TCNT has overflowed from H'FF

to H'00.

Bit 7

OVF

Description

[Clearing conditions]

• Write 0 in the TME bit

• Read TCSR when OVF = 1*, then write 0 in OVF

(Initial value)

[Setting condition]

When TCNT overflows (changes from H'FF to H'00)

(When internal reset request generation is selected in watchdog timer mode, OVF is

cleared automatically by the internal reset.)

Note:

When OVF flag is polled and the interval timer interrupt is disabled, OVF=1 must be

read at last twice.

Bit 6—Timer Mode Select (WT/

IT): Selects whether the WDT is used as a watchdog timer or

interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request

(WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates a reset or NMI

interrupt when TCNT overflows. When internal reset is selected in watchdog timer mode, a low-

level signal is output from the

RESO pin.

Bit 6

WT/

Description

Interval timer mode: Sends the CPU an interval timer interrupt request (WOVI) when

TCNT overflows

(Initial value)

Watchdog timer mode: Generates a reset or NMI interrupt when TCNT overflows

At the same time, a low-level signal is output from the

RESO pin (when internal reset

is selected)

Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.

Bit 5

TME

Description

TCNT is initialized to H'00 and halted

(Initial value)

TCNT counts

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