HD64F2149YV datasheet(440/1075 Pages) RENESAS

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Section 14 Watchdog Timer (WDT)

Rev. 3.00 Jan 18, 2006 page 412 of 1044

REJ09B0280-0300

14.1.4

The WDT has four registers, as summarized in table 14.2. These registers control clock selection,

WDT mode switching, the reset signal, etc.

Table 14.2

WDT Registers

Address*

Channel

Name

Abbreviation

R/W

Initial Value

Write*

Read

Timer control/status

TCSR0

R/(W)*

H'00

H'FFA8

Timer counter 0

TCNT0

R/W

H'00

H'FFA8

H'FFA9

Timer control/status

TCSR1

R/(W)*

H'00

H'FFEA

Timer counter 1

TCNT1

R/W

H'00

H'FFEA

H'FFEB

Common

System control

SYSCR

R/W

H'09

H'FFC4

Notes: 1. Lower 16 bits of the address.

2. For details of write operations, see section 14.2.4, Notes on Register Access.

3. Only 0 can be written in bit 7, to clear the flag.

14.2

14.2.1

Timer Counter (TCNT)

R/W

Bit

Initial value

Read/Write

TCNT is an 8-bit readable/writable* up-counter.

When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal

clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from

H'FF to H'00), the OVF flag in TCSR is set to 1. Watchdog timer overflow signal (

RESO) output,

an internal reset, NMI interrupt, interval timer interrupt (WOVI), etc., can be generated, depending

on the mode selected by the WT/

IT bit and RST/NMI bit.

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