HD64F2149YV datasheet(443/1075 Pages) RENESAS

443 / 1075 page

Section 14 Watchdog Timer (WDT)

Rev. 3.00 Jan 18, 2006 page 415 of 1044

REJ09B0280-0300

TCSR0 Bit 4—Reset Select (RSTS): Reserved. This bit should not be set to 1.

TCSR1 Bit 4—Prescaler Select (PSS): Selects the input clock source for TCNT in WDT1. For

details, see the description of the CKS2 to CKS0 bits below.

Bit 4

PSS

Description

TCNT counts

φ-based prescaler (PSM) divided clock pulses

(Initial value)

TCNT counts

SUB-based prescaler (PSS) divided clock pulses

Bit 3—Reset or NMI (RST/

NMI

NMI): Specifies whether an internal reset or NMI interrupt is

requested on TCNT overflow in watchdog timer mode.

Bit 3

RST/

NMI

Description

An NMI interrupt is requested

(Initial value)

An internal reset is requested

Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select an internal clock source,

obtained by dividing the system clock (

φ), or subclock (φ

SUB) for input to TCNT.

• WDT0 input clock selection

Bit 2

Bit 1

Bit 0

Description

CKS2

CKS1

CKS0

Clock

Overflow Period* (when

φφφφ = 10 MHz)

φ/2 (Initial value)

51.2 µs

φ/64

1.6 ms

φ/128

3.2 ms

φ/512

13.1 ms

φ/2048

52.4 ms

φ/8192

209.7 ms

φ/32768

838.9 ms

φ/131072

3.36 s

Note:

The overflow period is the time from when TCNT starts counting up from H'00 until

overflow occurs.

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