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GD32H757VMT7 Folha de dados(PDF) 138 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD32H757VMT7 Folha de dados(HTML) 138 Page - GigaDevice Semiconductor (Beijing) Inc. |
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138 / 151 page ![]() GD32H757xx Datasheet 137 Symbol Parameter Conditions Min Max Unit TIMER23 TIMER50 & TIMER51 — 64 bit tCOUNTER 16-bit counter clock period when internal clock is selected — 1 65536 tTIMERxCLK fTIMERxCLK = 300 MHz 0.0033 218.45 μs 32-bit counter clock period when internal clock is selected — 1 4294967296 tTIMERxCLK fTIMERxCLK = 300 MHz 0.0033 14316557.65 μs 64-bit counter clock period when internal clock is selected — 1 18446744073709551616 tTIMERxCLK fTIMERxCLK = 300 MHz 0.0033 61489146912365172.05 μs tMAX_COUNT Maximum possible count ( 16-bit) — — 65536x65536 tTIMERxCLK fTIMERxCLK = 300 MHz — 14.3 s Maximum possible count (32-bit) — — 4294967296x65536 tTIMERxCLK fTIMERxCLK = 300 MHz — 938249.9 s Maximum possible count (64-bit) — — 18446744073709551616x65536 tTIMERxCLK fTIMERxCLK = 300 MHz — 1119375758902.4 h (1) Value guaranteed by design, not 100% tested in production. 4.35. DCI characteristics Table 4-81. DCI characteristics(1) Symbol Parameter Min Max Unit Frequency ratio DCI_PIXCLK /fHCLK — 0.4 DCI_PIXCLK Pixel clock input — 160 MHz DPixel Pixel clock input duty cycle 30 70 % tsu(DATA) Data input setup time 2 — ns th(DATA) Data output valid time 1 — ns tsu(HSYNC) DCI_HS input setup time 2 — ns tsu(VSYNC) DCI_VS input setup time 2 — ns th(HSYNC) DCI_HS input hold time 1 — ns th(VSYNC) DCI_VS input hold time 1 — ns (1) Value guaranteed by design, not 100% tested in production. |
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