BQ25708 datasheet(67/77 Pages) TI2

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bq25708

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SLUSCU2 – NOVEMBER 2017

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11 Layout

11.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the

components to minimize high frequency current path loop (see Layout Example section) is important to prevent

electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for

proper layout. Layout PCB according to this specific order is essential.

1. Place the input capacitor as close as possible to the supply of the switching MOSFET and ground

connections. Use a short copper trace connection. These parts must be placed on the same layer of PCB

using vias to make this connection.

2. The device must be placed close to the gate pins of the switching MOSFET. Keep the gate drive signal

traces short for a clean MOSFET drive. The device can be placed on the other side of the PCB of switching

MOSFETs.

3. Place an inductor input pin as close as possible to the output pin of the switching MOSFET. Minimize the

copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to

carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic

capacitance from this area to any other trace or plane.

4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense

leads connected across the sensing resistor back to the device in same layer, close to each other (minimize

loop area) and do not route the sense leads through a high-current path (see Figure 50 for Kelvin connection

for best current accuracy). Place a decoupling capacitor on these traces next to the device.

5. Place an output capacitor next to the sensing resistor output and ground.

6. Output capacitor ground connections must be tied to the same copper that connects to the input capacitor

ground before connecting to system ground.

7. Use a single ground connection to tie the charger power ground to the charger analog ground. Just beneath

the device, use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise

coupling.

8. Route analog ground separately from power ground. Connect analog ground and connect power ground

separately. Connect analog ground and power ground together using power pad as the single ground

connection point. Or using a 0-Ω resistor to tie analog ground to power ground (power pad should tie to

analog ground in this case if possible).

9. Decoupling capacitors must be placed next to the device pins. Make trace connection as short as possible.

10. It is critical that the exposed power pad on the backside of the device package be soldered to the PCB

ground.

11. The via size and number should be enough for a given current path. See the EVM design (SLUUBG6) for

the recommended component placement with trace and via locations. For the WQFN information, see

SLUA271.

BQ25708 Folha de dados(PDF) 67 Page - Texas Instruments