BQ25708 datasheet(5/77 Pages) TI2

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bq25708

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SLUSCU2 – NOVEMBER 2017

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Pin Functions (continued)

I/O

DESCRIPTION

NAME

NUMBER

CMPIN

Input of independent comparator. The independent comparator compares the voltage sensed

on CMPIN pin to internal reference, and its output is on CMPOUT pin. Internal reference,

output polarity and deglitch time is selectable by SMBus. With polarity HIGH

(REG0x30[6]=1), place a resistor between CMPIN and CMPOUT to program hysteresis. With

polarity LOW (REG0x30[6]=0), the internal hysteresis is 100 mV. If the independent

comparator is not in use, tie CMPIN to ground.

CMPOUT

Open-drain output of independent comparator. Place pullup resistor from CMPOUT to pullup

supply rail. Internal reference, output polarity and deglitch time are selectable by SMBus.

COMP2

Buck boost converter compensation pin 2. Refer to bq25700 EVM schematic for COMP2 pin

RC network.

COMP1

Buck boost converter compensation pin 1. Refer to bq25700 EVM schematic for COMP1 pin

RC network.

Not Connected

HIDRV1

Buck mode high side power MOSFET (Q1) driver. Connect to high side n-channel MOSFET

gate.

HIDRV2

Boost mode high side power MOSFET(Q4) driver. Connect to high side n-channel MOSFET

gate.

IADPT

Buffered adapter current output. V(IADPT) = 20 or 40 × (V(ACP) – V(ACN)). With ratio selectable

in REG0x12[4]. Place a resistor from the IADPT pin to ground corresponding to inductor in

use. For 2.2 µH, the resistor is 100 kΩ. Place 100-pF or less ceramic decoupling capacitor

from IADPT pin to ground. IADPT output voltage is clamped below 3.3 V.

IBAT

Buffered battery current selected by SMBus. V(IBAT) = 8 or 16 × (V(SRP) – V(SRN)) for charge

current, or V(IBAT) = 8 or 16 × (V(SRN) – V(SRP)) for discharge current, with ratio selectable in

REG0x12[3]. Place 100-pF or less ceramic decoupling capacitor from IBAT pin to ground.

This pin can be floating if not in use. Its output voltage is clamped below 3.3 V.

ILIM_HIZ

Input current limit input. Program ILIM_HIZ voltage by connecting a resistor divider from

supply rail to ILIM_HIZ pin to ground. The pin voltage is calculated as: V(ILIM_HIZ) = 1 V + 40

× IDPM × RAC, in which IDPM is the target input current. The input current limit used by the

charger is the lower setting of ILIM_HIZ pin and REG0x3F(). When the pin voltage is below

0.4 V, the device enters Hi-Z mode with low quiescent current. When the pin voltage is

above 0.8 V, the device is out of Hi-Z mode.

LODRV1

Buck mode low side power MOSFET (Q2) driver. Connect to low side n-channel MOSFET

gate.

LODRV2

Boost mode low side power MOSFET (Q3) driver. Connect to low side n-channel MOSFET

gate.

PGND

GND

Device power ground.

PROCHOT

Active low open drain output of processor hot indicator. It monitors adapter input current,

battery discharge current, and system voltage. After any event in the PROCHOT profile is

triggered, a pulse is asserted. The minimum pulse width is adjustable in REG0x33[5:2].

PSYS

Current mode system power monitor. The output current is proportional to the total power

from the adapter and battery. The gain is selectable through SMBus. Place a resistor from

PSYS to ground to generate output voltage. This pin can be floating if not in use. Its output

voltage is clamped below 3.3 V. Place a capacitor in parallel with the resistor for filtering.

REGN

PWR

6-V linear regulator output supplied from VBUS or VSYS. The LDO is active when VBUS

above UVLO. Connect a 2.2- or 3.3-μF ceramic capacitor from REGN to power ground.

REGN pin output is for power stage gate drive.

SCL

SMBus clock input. Connect to clock line from the host controller or smart battery. Connect a

10-kΩ pullup resistor according to SMBus specifications.

SDA

I/O

SMBus open-drain data I/O. Connect to data line from the host controller or smart battery.

Connect a 10-kΩ pullup resistor according to SMBus specifications.

SRN

PWR

Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well.

Connect SRN pin with optional 0.1-μF ceramic capacitor to GND for common-mode filtering.

Connect a 0.1-μF ceramic capacitor from SRP to SRN to provide differential mode filtering.

The leakage current on SRP and SRN are matched. For reverse battery plug-in protection,

10-Ω series resistors are placed on SRP and SRN.

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