SPSB100 datasheet(41/213 Pages) STMICROELECTRONICS

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3.11.3

Reaction on error

When an error is detected by the MCU fault monitoring, the NRST pin is asserted low, the status bit FCCUFAIL is

set, the state machine reacts as described in the Section 3.6.2.2: Watchdog trig and FCCU monitor faults

management. The live status bit FIN1_STATE shows the current state of FIN1 input.

To properly restart FCCU block after a FCCUFAIL detection, MCU has to write FCCU_ENA = 0, clear the

FCCUFAIL flag and re-enable the monitoring by setting FCCU_ENA = 1.

The live bit FCCU_ENA_STATUS reflects the state of the FCCU block.

3.12

High-side output OUT_HS

In active, FULL-POWER or LOW-POWER modes, and in DEEP_SLEEP states the high side driver output

OUT_HS can be configured for supplying external loads or contacts.

The high side output can be either controlled:

•

Permanently ON (OUTHS_[1..0] = 01)

•

Permanently OFF (OUTHS_[1..0] = 00)

•

Through an internal timer (OUTHS_[1..0] = 1x)

In timer mode configuration (when TIMER_ENA = 1) the activation period can be configured through the bits

T1_PER [2..0] in the following range {10, 20, 50,100, 200, 500, 1000, 2000 ms}.

On-time is configurable through bits T1_ENA[1..0] in the following range {0.1, 0.3, 1, 10, 20 ms}.

In case the wake-up inputs WU and IGN are configured in cyclic sense mode(WU_FILT = 1, IGN_FILT = 1)), the

capture of their input state is synchronized with the high-side timer mode:

•

A switched ON delay time tDON_OUT_HS is applied after the high-side is turned ON.

•

A switched OFF delay time tDOFF_OUT_HS is applied after the high-side is turned OFF.

•

A fixed filter time of tWU_cyc is applied after blanking time has elapsed before refreshing the WU_WAKE or

IGN_WAKE.

•

In case of status change detection between the previous and the new captured state, the status bits

WU_WAKE and IGN_WAKE will be set in the status register. Depending on the dedicated settings applied

on each wake-up input, wake-up detection could wake-up the SPSB100 and/or generate an interrupt signal

on the IRQ pin.

In case of overcurrent, detection is done by OUTHS_OC bit, OUTHS driver is switched off after filter time

toc_out_hs and an IRQ is generated except if MASK_OUTHS_IRQ is set.

After an OC detection, OUTHS can be re-enabled by clearing the status bit OUTHS_OC.

In case of open load, detection is done by OUTHS_OL bit, an IRQ is generated except if MASK_OUTHS_IRQ is

set.

The live bit OUTHS_ENA_STATUS reflects the state of OUTHS output.

Note:

The high-side driver OUT_HS is intended to drive resistive loads only. Therefore, only a limited energy (E < 1

mJ) can be dissipated by the internal ESD-diodes in freewheeling condition. For inductive loads (L > 100 μH) an

external freewheeling diode connected between GND and the OUT_HS pin is required.

3.13

Fail-safe output - NFSO1

NFSO1 is asserted low when a fault event is detected. The objective of this pin is to drive an electrical safe

circuitry independent from the MCU to deactivate the whole system and set the ECU in a protected and known

state.

The NFSO1 pin is an open drain output. An external pull-up circuitry must be connected to VIO or VBAT.

The NFSO1 pin is controlled by an asynchronous OR of:

•

Asynchronous supervisor of internal voltage reference. When a difference between the main and

monitoring voltage reference is detected the NFSO1 pin is asserted low.

•

Synchronous monitor of main oscillator. When an oscillator frequency drift or a stuck at is detected the

NFSO1 pin is asserted low.

•

When a watchdog or FCCU fail occurs the NFSO1 pin is asserted low.

•

The SPI control bit NFSO_ASSERT_LOW (only after SPI_PROTECT_ACCESS has been set):

–

NFSO_ASSERT_LOW = 1: pin is asserted low.

–

NFSO_ASSERT_LOW = 0: pin is in high impedance. Its level is defined by external pull-up.

SPSB100

Functional description

DS14640 - Rev 2

page 41/213

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