SPSB100 datasheet(49/213 Pages) STMICROELECTRONICS

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Protection, diagnosis and monitoring signals

4.1

Supply monitoring

4.1.1

VS pin

The battery line is monitored through a VS pin.

The VS input voltage is monitored through analog comparators and the ADC:

•

VS input voltage can be read back by SPI access, by VS[9..0].

•

The ADC is used to detect under voltage early warnings (flagged by VS_UV_EW bit).

The thresholds are programmable by SPI (VS_UV_EW_TH[4..0]) and an interrupt is issued when thresholds are

crossed except if MASK_VS_EW_IRQ is set.

4.1.2

FBB pin

The FBB input voltage is monitored through analog comparators and the ADC:

•

Analog comparator is used to detect over and undervoltages. The reaction to a FBB voltage fault is

described in the Section 3.6.2.6: FBB voltage drop management.

•

An analog comparator is used to detect over voltage. The flag is FBB_OV and generates an IRQ except if

MASK_FBB_OV_IRQ is set. The state machine executes a power down sequence to enter in DEEP-

SLEEP.

•

An analog comparator is used to detect undervoltage. The flag is FBB_UV and generates an IRQ except if

MASK_FBB_UV_IRQ is set. The state machine executes a power down sequence to enter in DEEP-

SLEEP.

•

The ADC is used to detect overvoltage early warnings (flagged by FBB_OV_EW bit).

•

The ADC is used to detect undervoltage early warnings (flagged by FBB_UV_EW bit).

•

The thresholds are programmable by SPI (FBB_OV_EW_TH[3..0]) and an interrupt is issued when

thresholds are crossed except if MASK_FBB_OV_EW_IRQ is set.

•

The thresholds are programmable by SPI (FBB_UV_EW_TH[3..0]) and an interrupt is issued when

thresholds are crossed, except if MASK_FBB_UV_EW_IRQ is set.

•

The result of ADC conversion is also readable back via SPI, by FBB[9..0].

4.1.3

VIO pin

VIO voltage is monitored through an analog comparator and digital communication is blocked if VIO voltage is

below VVIO_UV threshold for a delay higher than TF_VIO_UV (flag is VIO_UV bit).

4.2

Regulators output voltage protection

The 3 BUCKs and LDO2 outputs are monitored through analog comparators to detect over and undervoltages.

(through BUCKx_UV, BUCKx_OV, LDO2_UV and LDO2_OV bits). The reaction to a fault is described in the

Section 3.6.2.5: Regulator faults management. In addition, LDO2 is also turned OFF when the tracked regulator is

turned OFF in reaction to a fault.

When a regulator is turned ON, by SPI or power-up sequence, a short to ground is detected if the output voltage

does not reach the power-good threshold in the time-out period (BUCKx_PG_TIMEOUT bit), in such case the

regulator is switched OFF.

In addition, when turned ON through the SPI, an interrupt is generated as soon as their output voltage reaches

the power-good threshold(BUCKx_PG and LDO2_PG bits).

Latent fault detection of OV, UV, PG analog comparators is insured by Analog-BIST.

Latent fault of regulator monitor handler is insured by Digital-BIST.

4.3

Boost and bypass Vds monitoring

The BOOST driver includes a comparator to monitor the voltage drop across the boost external transistor. The

voltage is monitored between DLB and GND pins.

SPSB100

Protection, diagnosis and monitoring signals

DS14640 - Rev 2

page 49/213

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