SPSB100 datasheet(31/213 Pages) STMICROELECTRONICS

31 / 213 page

3.6.3

States and transitions description

The following figure shows the entire state machine.

Figure 21. State machine

ACTIVE state

WD trigger OK*

LOW-POWER

mode

FULL-POWER

mode

SPI cmd

WD trigger OK*

Power

OFF

START -UP

state

Execute

Power-Up

sequence

Finished OK

any

STATE

DEEP-SLEEP

state

INIT

state

Digital Reset

Safety checks NOK

NOK

Execute

Power-Down

sequence

PG_TimeOut reached

OR REGfail & GoREC=1

(retry ≤ 3)

OR (for_ever = 1) ?

Retry loop

PM100

unpowered

Wake-up

event

(WD trigger fail)*

OR FCCU fail

REC-1

state

Wake-up

event

NRESET asserted 4ms

for WD fail or 6ms for

FCCU fail, then WD

restarted in L.O.W.*

NFSO &

NRESET

asserted,

FCCU

disabled

Execute Power -

Up sequence

(NRESET not

deasserted)

SPI cmd “DO_POWER_CYCLE”

OR CENTRAL_TSD

OR REG fail & GoREC=1

OR VFBB ≤ VFBB_UV_F

OR VFBB ≥ VFBB_OV

Execute

Power-Down

sequence

Finished OK

REC-2

state

Wake-up event

OR TSDC event & not T ° cooled down

TSD event & cnt ≥ 3

Execute

Power-Down

sequence

SPI cmd “DO_POWER_DOWN”

OR CENTRAL_GNDLOST

OR WD trigger fail & cnt ≥ 15

SPI cmd “DO_POWER_CYCLE”

OR CENTRAL_TSD

OR REG fail & GoREC=1

OR (WD trigger fail)* & cnt = 8

OR VFBB ≤ VFBB_UV_F

OR VFBB ≥ VFBB_OV

SPI cmd “DO_POWER_DOWN”

OR CENTRAL_GNDLOST

NFSO asserted

Set SPI error flag

AND sends IRQ

AND if unmasked then turns OFF

failing reg. with active discharge

REG fail

& GoREC=0

Back to

previous state

(WD LOW trigger OK)*

AND error cleared

NFSO asserted

START -SM

Retry loop

SPI cmd “DO_POWER_CYCLE” @ previous state

OR VFBB ≤ VFBB_UV_F OR VFBB ≥ VFBB_OV

OR TSD event & T ° cooled down & cnt < 3

OR REG fail & GoREC=1 (except TSD)

OR (WD failed)* @ REC -1 & cnt = 8

PG_TimeOut reached

OR REGfail & GoREC=1

> V

PORVS_R

VVS < VPORVS_F

Safety checks OK

AND VFBB_OK_R < VFBB < VFBB_OV

AND VVREG_UV < VVREG < VVREG_OV

* when LOW_SET = 1111, watchdog service is disabled

(WD trigger fail)* & cnt !=8,15

OR (FCCU enabled & fail)

SPSB100 states can be read by status register bits DEV_STATE.

3.6.3.1

Power-OFF state

Power-OFF state is the default state when SPSB100 is not powered.

This state is entered unconditionally when VS pin voltage drops below VPORVS_F.

3.6.3.2

START-UP state

START-UP state is entered from Power-OFF state when VS pin voltage reaches VPORVS_R.

In this state internal power supplies are established, and the digital core reset is released.

SPSB100 transits to START-SM state.

3.6.3.3

START-SM state

START-SM state is entered after the START-UP completion when the digital core reset is released.

In this state oscillators start and the main state machine is executed. It is possible to enter in USER-NVM

programming mode, refers to the Section 3.8: User's NVM modification procedure for details.

When USER-NVM programming mode is not entered, SPSB100 transits automatically from START-SM to INIT

state.

3.6.3.4

INIT state

The INIT state is entered:

•

After completion of START-SM state and NVM is loaded without error.

•

From a DEEP-SLEEP state upon a wake-up event.

SPSB100

Functional description

DS14640 - Rev 2

page 31/213

SPSB100 Folha de dados(PDF) 31 Page - STMicroelectronics

SPSB100 Folha de dados(HTML) 31 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL