SPSB100 datasheet(47/213 Pages) STMICROELECTRONICS

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SPI status bit name

IRQ generated

IRQ SPI mask name

VS_UV_EW

MASK_VS_EW_IRQ

WD_ENA_ECHO_ERROR

MASK_WD_ENA_ECHO_ERROR_IRQ

WU_WAKE

Not WU_ENA

FP_READY

Not maskable

LBIST_STOPPED

Not maskable

LP_READY

MASK_LP_READY_IRQ

Interrupt is a NOR of all information except if some masks are set. A read and clear of all setted flags is needed to

allow the IRQ pin to be set high.

Interrupt output pin indicates:

•

Warnings and errors which must be reported to the MCU.

•

Confirmation of a requested action from the MCU.

3.15

Reset output - NRST

The NRST pin is an open-drain with an internal pull-up for the echo-generation. An external pull-up to VIO level

close to MCU is strongly recommended.

The aim of NRST output is to drive the MCU NRST input pin.

The NRST is released after a proper power-up sequence before reaching the RECOVERY-1 state, and is

asserted low after tNRST_rt, in case of error as described in the Section 3.6.3: States and transitions description.

3.16

10-bit ADC

In ACTIVE – FULL-POWER mode and RECOVERY-1 state the voltage signals VS, FBB, WU, IGN, TH_CL0,

TH_CL1, TH_CL2, TH_CL3, and TH_CL4 are read out sequentially. Related bit names in the status register are

VS[0..9], FBB[0..9], WU[0..9], IGN[0..9], TEMP_CL0[0..9], TEMP_CL1[0..9], TEMP_CL2[0..9], TEMP_CL3[0..9]

and TEMP_CL4[0..9].

The voltage signals are multiplexed to an ADC. The ADC is realized as a 10-Bit SAR. Each channel is converted

with a conversion time tcon, therefore an update of the ADC value is available every tcon * 13.

The voltage measurement on VS, FBB, WU and IGN can be calculated from the binary coded register value using

the following formula:

Decimal code = (VIN/LSB_V ) – 1

The temperature measurement on TEMP_CL0-4 can be calculated from the binary coded register value using the

following formula:

Decimal code = ((355 – Tj)/LSB_T) – 1

In case of WU, or IGN, is directly connected to battery line, the input must be protected by a series resistance of

typical 1 kΩ to sustain reverse battery condition.

3.17

SW-Debug mode

The SW-Debug mode is intended for software development. In SW-Debug mode SPSB100 is fully operational

except that the watchdog is not started and consequently does not monitor proper watchdog trig.

To set the device in SW-DEBUG mode, the SWDBG pin must be shorted to VIO before a power-up sequence

(cold start or wake up from DEEP-SLEEP). With such setting the device executes the power-up sequence and,

instead of reaching RECOVERY-1 state, the device transits to SWDBG state.

In SWDBG state the timeout tSWDBG_TO is launched.

The timeout is used to prevent the system from being stuck in SWDBG state:

If the timeout expires, then SW-Debug mode entry is canceled. The device transits to RECOVERY-1 state and

starts the watchdog with a long open window. Status register bit SWDBG_VIO is set, an IRQ (maskable by

MASK_SWDBG_VIO_IRQ) is generated to indicate that SWDBG pin is shorted to VIO.

If the short to VIO is removed before timeout expiration then the device transits to RECOVERY-1 state, the

watchdog is disabled. To transit to ACTIVE-FULL-POWER mode the software must clear error flags and set

WD_TRIG, this is the unique access to WD_TRIG that the software must handle in SW-Debug mode.

SPSB100

Functional description

DS14640 - Rev 2

page 47/213

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