SPSB100 datasheet(63/213 Pages) STMICROELECTRONICS

63 / 213 page

<Device No. 4>: 4EH (ASCII code for N)

<Device No. 5>: 01H: SPSB100B and SPSB100P

5.2.3.1.2

SPI modes

By reading out the <SPI Mode> register general information of SPI usage of the device application registers can

be read.

Table 16. SPI mode register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FL2

FL1

FL0

SPI8

<SPI Mode>: 32H (no burst mode available, 32 bit, CRC used)

5.2.3.1.3

CRC

SDI:

The CRC check is performed on the complete communication frame using the polynomial (X4 + X + 1).

The frame is valid only if the result of the CRC check is equal to ‘0’. If not, the frame is rejected and a SPIE bit is

set.

SDO:

CRC is calculated on GSB + data -4 bit and the 4-bits result is saved in data LSB_3 to data LSB_0.

Figure 36. CRC (cyclic redundancy check) calculation

GSB

Data

CRC3(*)

CRC2(*)

CRC1(*)

CRC0(*)

CRC check

Exceptions:

The CRC field is not inserted when device information is read in ROM registers.

5.2.3.2

Watchdog definition

For more details, refer to the Section 3.10: Configurable time-out window watchdog.

The watchdog default settings can be read out via the device information registers.

Table 17. WD Type/Timing

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Watchdog long open window WT[5:0]

Open window OW[2:0]

Closed window CW[2:0]

<WD Type 1>: long open window: reflects the value of LOW_SET(1:0) bits of USER-NVM

<WD Type 2>: 91H (open window. 10 ms, closed window: 5 ms)

SPSB100

Serial peripheral interface (SPI)

DS14640 - Rev 2

page 63/213

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