SPSB100 datasheet(20/213 Pages) STMICROELECTRONICS

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The BUCK3 converter is similar to BUCK1 but with double current capability. Moreover, if the output voltage is

configured at 0.98 V, a further SPI fine-tuning in steps of 10 mV is available (BUCK3_FTUNE[2..0] control bits),

covering the range between 0.95 V and 1.01 V.

Output voltages are programmable via USER-NVM through the bit BUCK3_PU_VALUE.

The spread spectrum feature is configurable by SPI bit BUCK3_SPREAD_ENA (disabled by default).

To limit emission in audio bandwidth, refresh frequency can be forced at 25 kHz by USER-NVM bit

BUCK3_REFRESH_FREQ set low (1 kHz when high).

BUCK3 can be disabled by the SPI bit VBUCK3_ENA. (only after SPI_PROTECT_ACCESS has been set.

BUCK3 must be disabled before entering in active low power mode and must not be enabled in this mode).

The live bit VBUCK3_ENA_STATUS reflects the state of BUCK3 output.

Note:

After the first power up is needed to align the live bit associated in DSR18 (VBUCK3_ENA_STATUS) with the

current value associated in DCR1.

The BUCK3 converter provides the following diagnostics:

•

UV detection to monitor the output voltage (flag is BUCK3_UV). BUCK3 is therefore switched off after

tbuck3_UV_TO except if SPI bit MASK_BUCK3_UV_POWER_OFF is set.

•

Undervoltage detection generates an IRQ except if MASK_BUCK3_IRQ is set.

•

OV detection to monitor the output voltage (flag is BUCK3_OV bit) BUCK3 is therefore switched off after

tbuck3_OV_TO. It must be read and cleared before switching ON the regulator by SPI bit VBUCK3_ENA to

allow a proper start-up (only when BUCK3 is not critical for MCU).

•

Overvoltage detection generates an IRQ except if MASK_BUCK3_IRQ is set.

•

Power-good used to signal BUCK power on success (flag is BUCK3_PG_OK bit and IRQ is generated

except if MASK_BUCK3_PG_IRQ is set):

–

If not, after TBUCK3_PG_TO timing, BUCK3 is switched off and flag BUCK3_PG_TIMEOUT is set.

•

Not successful power-good detection generates an IRQ except if MASK_BUCK3_PG_TIMEOUT_IRQ is

set.

•

Configurable overcurrent protection voltage (flag is BUCK3_OC bit). BUCK3 is therefore switched off after

tbuck3_OC_TO except if MASK_BUCK3_OC_POWER_OFF is set.

•

Overcurrent detection generates an IRQ except if MASK_BUCK3_OC_IRQ is set.

•

Warning temperature detection by a local thermal sensor (flag is TW_CL3).

•

Warning temperature detection generates an IRQ except if MASK_CL3_TW_IRQ is set.

•

Overtemperature detection by local thermal sensor (flag is TSD_CL3, see also the

Section 4.7: Temperature monitoring) and BUCK3 is switched off.

•

BUCK3 internal regulators detection, flag is BUCK3_INT_FAIL and the BUCK3 is switched off.

•

Internal fail generates an IRQ except if MASK_BUCK3_IRQ is set.

•

After a fault detection (UV, OV,OC, INT_FAIL, TSD_CL3 or PG timeout), BUCK3 can be re

‑enabled by

setting BUCK3_ENA = 0 followed by BUCK3_ENA = 1.

In active and REC-1 states, when BUCK3_REGFAIL_GO_REC is set at 1 in USER-NVM, in case of PG timeout,

OV, UV, OC, INT_FAIL or TSD events the device executes a power down sequence, enters in REC-2 state and

makes an automatic retry. PG_TIMEOUT, OV, UV, OC, INT_FAIL or TSD flags are not blocking to re-enable the

BUCK3 after a fail event.

It is not recommended to use MASK_BUCK3_OC_POWER_OFF and MASK_BUCK3_UV_POWER_OFF in the

same time.

3.4

Linear voltage regulators

3.4.1

LDO1

The LDO1 is dedicated to supply external loads. It is supplied by FBB pin. LDO1 has a 5 V output and 120 mA

current capability.

It can be enabled/disabled through the LDO1_ENA control bit (only after SPI_PROTECT_ACCESS has been set).

The voltage regulator is protected against undervoltage (flag is LDO1_UV) and LDO1 is switched off.

The undervoltage detection generates an IRQ except if it is masked with MASK_LDO1_IRQ the live bit

LDO1_ENA_STATUS reflects the state of LDO1 output.

SPSB100

Functional description

DS14640 - Rev 2

page 20/213

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